From df3af8018e5a252f7c4e8f52b872263c8ab375cc Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 16 Aug 2006 14:16:52 -0700 Subject: Minor regression fixes. src/python/m5/objects/BaseCPU.py: bug fix tests/SConscript: fix up diff ignore strings to reflect changes in m5 output --HG-- extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128 --- src/python/m5/objects/BaseCPU.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/python/m5/objects/BaseCPU.py') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 7906156a2..01458aeb4 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -49,5 +49,5 @@ class BaseCPU(SimObject): self.toL2Bus = Bus() self.connectMemPorts(self.toL2Bus) self.l2cache = l2c - self.l2cache.cpu_side = toL2Bus.port + self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] -- cgit v1.2.3