From 8ade33d324218737c815935120307153975eeadc Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 7 Jul 2006 17:33:24 -0400 Subject: Support Ron's changes for hooking up ports. src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918 --- src/python/m5/objects/O3CPU.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 9ccbdcf53..6ba62b47e 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -10,6 +10,8 @@ class DerivO3CPU(BaseCPU): checker = Param.BaseCPU(NULL, "checker") cachePorts = Param.Unsigned("Cache Ports") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") renameToFetchDelay = Param.Unsigned("Rename to fetch delay") -- cgit v1.2.3 From 43245d9c2f3986430c1fbc4a09ee90096f6d3f30 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 7 Jul 2006 18:24:13 -0400 Subject: Support for recent port changes. src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. --HG-- extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891 --- src/python/m5/objects/OzoneCPU.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py index 8aff89203..88fb63c74 100644 --- a/src/python/m5/objects/OzoneCPU.py +++ b/src/python/m5/objects/OzoneCPU.py @@ -9,6 +9,9 @@ class DerivOzoneCPU(BaseCPU): checker = Param.BaseCPU("Checker CPU") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") backEndWidth = Param.Unsigned("Back end width") -- cgit v1.2.3 From fcaafdc48cc624825760cb3ba7bbc28e5db6acfa Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 10 Jul 2006 15:40:28 -0400 Subject: Add parameters for backwards and forwards sizes for time buffers. src/base/timebuf.hh: Add a function to return the size of the time buffer. --HG-- extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4 --- src/python/m5/objects/O3CPU.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 6ba62b47e..d6bc454ad 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -53,6 +53,9 @@ class DerivO3CPU(BaseCPU): trapLatency = Param.Tick("Trap latency") fetchTrapLatency = Param.Tick("Fetch trap latency") + backComSize = Param.Unsigned("Time buffer size for backwards communication") + forwardComSize = Param.Unsigned("Time buffer size for forward communication") + predType = Param.String("Branch predictor type ('local', 'tournament')") localPredictorSize = Param.Unsigned("Size of local predictor") localCtrBits = Param.Unsigned("Bits per counter") -- cgit v1.2.3