From 05c487ef3ce6eb015bc8716df7e9caeedfe520da Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 17 Oct 2006 21:15:11 -0700 Subject: Enable MP systems via cmd-line flag in fs.py. configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now). --HG-- extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf --- src/python/m5/objects/AlphaConsole.py | 2 +- src/python/m5/objects/IntrControl.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py index 1c71493b1..f968aaa40 100644 --- a/src/python/m5/objects/AlphaConsole.py +++ b/src/python/m5/objects/AlphaConsole.py @@ -4,7 +4,7 @@ from Device import BasicPioDevice class AlphaConsole(BasicPioDevice): type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.any, "Processor") + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") sim_console = Param.SimConsole(Parent.any, "The Simulator Console") system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py index 95be0f4df..a7cf5cc84 100644 --- a/src/python/m5/objects/IntrControl.py +++ b/src/python/m5/objects/IntrControl.py @@ -3,4 +3,4 @@ from m5.params import * from m5.proxy import * class IntrControl(SimObject): type = 'IntrControl' - cpu = Param.BaseCPU(Parent.any, "the cpu") + cpu = Param.BaseCPU(Parent.cpu[0], "the cpu") -- cgit v1.2.3 From 6cd187e1f066b084740b4b202f1de644ba06f299 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 18 Oct 2006 08:16:22 -0700 Subject: Get rid of obsolete in-cache copy support. --HG-- extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25 --- src/python/m5/objects/BaseCache.py | 1 - 1 file changed, 1 deletion(-) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index db58a177f..773a11bea 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -14,7 +14,6 @@ class BaseCache(MemObject): "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") hash_delay = Param.Int(1, "time in cycles of hash access") lifo = Param.Bool(False, "whether this NIC partition should use LIFO repl. policy") -- cgit v1.2.3 From 28e9641c2cf063d8ee1eba9f440dfcda9c82d965 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 20 Oct 2006 13:01:21 -0400 Subject: Use fixPacket function everywhere. Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device --HG-- extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e --- src/python/m5/objects/MemTest.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py index 83399be80..1219ddd4d 100644 --- a/src/python/m5/objects/MemTest.py +++ b/src/python/m5/objects/MemTest.py @@ -13,6 +13,7 @@ class MemTest(SimObject): percent_reads = Param.Percent(65, "target read percentage") percent_source_unaligned = Param.Percent(50, "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") percent_uncacheable = Param.Percent(10, "target uncacheable percentage") progress_interval = Param.Counter(1000000, -- cgit v1.2.3