From d9172c8f462511cde474040581063180be18540a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 5 Oct 2006 16:26:16 -0400 Subject: Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets. --HG-- extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39 --- src/python/m5/objects/Bus.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index f6828a0d5..b7c55990c 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -6,3 +6,5 @@ class Bus(MemObject): port = VectorPort("vector port for connecting devices") default = Port("Default port for requests that aren't handeled by a device.") bus_id = Param.Int(0, "blah") + clock = Param.Clock("1GHz", "bus clock speed") + width = Param.Int(64, "bus width (bits)") -- cgit v1.2.3 From d3fba5aa30adfb006b99895e869ed175213d0134 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 8 Oct 2006 10:53:24 -0700 Subject: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be --- src/python/m5/objects/BaseCPU.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 0b887cceb..b6dc08e46 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -11,10 +11,11 @@ class BaseCPU(SimObject): mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") + cpu_id = Param.Int("CPU identifier") + if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") - cpu_id = Param.Int(-1, "CPU identifier") else: workload = VectorParam.Process("processes to run") -- cgit v1.2.3 From a82f017591ecb78cb098e38314d87d64fcaaa37f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 8 Oct 2006 18:44:49 -0400 Subject: bus changes src/mem/bus.cc: src/mem/bus.hh: minor fix and some formatting changes src/python/m5/objects/Bus.py: changed bits to bytes --HG-- extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5 --- src/python/m5/objects/Bus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index b7c55990c..6710111e5 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -7,4 +7,4 @@ class Bus(MemObject): default = Port("Default port for requests that aren't handeled by a device.") bus_id = Param.Int(0, "blah") clock = Param.Clock("1GHz", "bus clock speed") - width = Param.Int(64, "bus width (bits)") + width = Param.Int(64, "bus width (bytes)") -- cgit v1.2.3 From 6c7ab02682aba37c173962ec907b97483625d18b Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 00:26:10 -0400 Subject: Update the Memtester, commit a config file/test for it. src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter. For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description --HG-- extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482 --- src/python/m5/objects/MemTest.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py index 97600768f..18aff03f4 100644 --- a/src/python/m5/objects/MemTest.py +++ b/src/python/m5/objects/MemTest.py @@ -1,13 +1,12 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * +from m5 import build_env + class MemTest(SimObject): type = 'MemTest' - cache = Param.BaseCache("L1 cache") - check_mem = Param.FunctionalMemory("check memory") - main_mem = Param.FunctionalMemory("hierarchical memory") max_loads = Param.Counter("number of loads to execute") memory_size = Param.Int(65536, "memory size") - percent_copies = Param.Percent(0, "target copy percentage") percent_dest_unaligned = Param.Percent(50, "percent of copy dest address that are unaligned") percent_reads = Param.Percent(65, "target read percentage") @@ -18,3 +17,6 @@ class MemTest(SimObject): progress_interval = Param.Counter(1000000, "progress report interval (in accesses)") trace_addr = Param.Addr(0, "address to trace") + + test = Port("Port to the memory system to test") + functional = Port("Port to the functional memory used for verification") -- cgit v1.2.3 From b9fb4d4870dd45c552fd4cd5e531e9626754f19f Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 9 Oct 2006 17:13:50 -0400 Subject: Make memtest work with 8 memtesters src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system --HG-- extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca --- src/python/m5/objects/PhysicalMemory.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index dd3ffd651..4e097543d 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -5,6 +5,7 @@ from MemObject import * class PhysicalMemory(MemObject): type = 'PhysicalMemory' port = Port("the access port") + functional = Port("Functional Access Port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") -- cgit v1.2.3