From c39aea440c884f0abb29ecc2293fd6df608bc00c Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Mon, 4 Sep 2006 17:14:07 -0700
Subject: More Python hacking to deal with config.py split and resulting
 recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
---
 src/python/m5/objects/AlphaConsole.py      | 3 ++-
 src/python/m5/objects/AlphaTLB.py          | 3 ++-
 src/python/m5/objects/BadDevice.py         | 2 +-
 src/python/m5/objects/BaseCPU.py           | 4 +++-
 src/python/m5/objects/BaseCache.py         | 2 +-
 src/python/m5/objects/Bridge.py            | 2 +-
 src/python/m5/objects/Bus.py               | 2 +-
 src/python/m5/objects/CoherenceProtocol.py | 3 ++-
 src/python/m5/objects/Device.py            | 3 ++-
 src/python/m5/objects/DiskImage.py         | 3 ++-
 src/python/m5/objects/Ethernet.py          | 4 +++-
 src/python/m5/objects/FUPool.py            | 3 ++-
 src/python/m5/objects/FuncUnit.py          | 3 ++-
 src/python/m5/objects/Ide.py               | 3 ++-
 src/python/m5/objects/IntrControl.py       | 4 +++-
 src/python/m5/objects/MemObject.py         | 3 ++-
 src/python/m5/objects/MemTest.py           | 3 ++-
 src/python/m5/objects/O3CPU.py             | 3 ++-
 src/python/m5/objects/OzoneCPU.py          | 2 +-
 src/python/m5/objects/Pci.py               | 4 +++-
 src/python/m5/objects/PhysicalMemory.py    | 3 ++-
 src/python/m5/objects/Platform.py          | 4 +++-
 src/python/m5/objects/Process.py           | 4 +++-
 src/python/m5/objects/Repl.py              | 3 ++-
 src/python/m5/objects/Root.py              | 3 ++-
 src/python/m5/objects/SimConsole.py        | 4 +++-
 src/python/m5/objects/SimpleDisk.py        | 4 +++-
 src/python/m5/objects/SimpleOzoneCPU.py    | 2 +-
 src/python/m5/objects/System.py            | 4 +++-
 src/python/m5/objects/Tsunami.py           | 3 ++-
 src/python/m5/objects/Uart.py              | 3 ++-
 31 files changed, 65 insertions(+), 31 deletions(-)

(limited to 'src/python/m5/objects')

diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
index 329b8c5bd..1c71493b1 100644
--- a/src/python/m5/objects/AlphaConsole.py
+++ b/src/python/m5/objects/AlphaConsole.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
 from Device import BasicPioDevice
 
 class AlphaConsole(BasicPioDevice):
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
index 11c1792ee..af7c04a84 100644
--- a/src/python/m5/objects/AlphaTLB.py
+++ b/src/python/m5/objects/AlphaTLB.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 class AlphaTLB(SimObject):
     type = 'AlphaTLB'
     abstract = True
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
index 186b733fa..919623887 100644
--- a/src/python/m5/objects/BadDevice.py
+++ b/src/python/m5/objects/BadDevice.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
 from Device import BasicPioDevice
 
 class BadDevice(BasicPioDevice):
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 41e90b12b..3dd0bda01 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 from m5 import build_env
-from m5.config import *
 from AlphaTLB import AlphaDTB, AlphaITB
 from Bus import Bus
 
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 497b2b038..db58a177f 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
 from MemObject import MemObject
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index c9e673afb..ee8e76bff 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
 from MemObject import MemObject
 
 class Bridge(MemObject):
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index e0278e6c3..f6828a0d5 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
 from MemObject import MemObject
 
 class Bus(MemObject):
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py
index 64b6cbacf..82adb6862 100644
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ b/src/python/m5/objects/CoherenceProtocol.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
 
 class CoherenceProtocol(SimObject):
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index f72c8e73f..3e9094e25 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
 from MemObject import MemObject
 
 class PioDevice(MemObject):
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index a98b35a4f..d0ada7ee1 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 class DiskImage(SimObject):
     type = 'DiskImage'
     abstract = True
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index fb641bf80..609a3dd6f 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 from m5 import build_env
-from m5.config import *
 from Device import DmaDevice
 from Pci import PciDevice, PciConfigData
 
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index cbf1089cf..4b4be79a6 100644
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 
 class FUPool(SimObject):
     type = 'FUPool'
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
index f61590ae9..f0ad55f7a 100644
--- a/src/python/m5/objects/FuncUnit.py
+++ b/src/python/m5/objects/FuncUnit.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 
 class OpType(Enum):
     vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index a8bd4ac5a..69681bdbd 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 from Pci import PciDevice, PciConfigData
 
 class IdeID(Enum): vals = ['master', 'slave']
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
index 514c3fc62..95be0f4df 100644
--- a/src/python/m5/objects/IntrControl.py
+++ b/src/python/m5/objects/IntrControl.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 class IntrControl(SimObject):
     type = 'IntrControl'
     cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
index d957dae17..8982d553d 100644
--- a/src/python/m5/objects/MemObject.py
+++ b/src/python/m5/objects/MemObject.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.SimObject import SimObject
 
 class MemObject(SimObject):
     type = 'MemObject'
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 9916d7cb4..97600768f 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 class MemTest(SimObject):
     type = 'MemTest'
     cache = Param.BaseCache("L1 cache")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 900bbf28c..5100c7ccb 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
 from m5 import build_env
-from m5.config import *
 from BaseCPU import BaseCPU
 from Checker import O3Checker
 
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 88fb63c74..8f25d77ed 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
 from m5 import build_env
-from m5.config import *
 from BaseCPU import BaseCPU
 
 class DerivOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index cc0d1cf4a..7c239d069 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 from Device import BasicPioDevice, DmaDevice, PioDevice
 
 class PciConfigData(SimObject):
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index bc427aa88..dd3ffd651 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
 from MemObject import *
 
 class PhysicalMemory(MemObject):
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
index 89fee9991..ab2083eea 100644
--- a/src/python/m5/objects/Platform.py
+++ b/src/python/m5/objects/Platform.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 class Platform(SimObject):
     type = 'Platform'
     abstract = True
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
index 0091d8654..08f8b6bce 100644
--- a/src/python/m5/objects/Process.py
+++ b/src/python/m5/objects/Process.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 class Process(SimObject):
     type = 'Process'
     abstract = True
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index 8e9f1094f..10892cf6f 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 class Repl(SimObject):
     type = 'Repl'
     abstract = True
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 33dd22620..f01fc06c4 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
 from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index 9e1452c6d..bdd7f246d 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 class ConsoleListener(SimObject):
     type = 'ConsoleListener'
     port = Param.TcpPort(3456, "listen port")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
index 44ef709af..099a77dbb 100644
--- a/src/python/m5/objects/SimpleDisk.py
+++ b/src/python/m5/objects/SimpleDisk.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 class SimpleDisk(SimObject):
     type = 'SimpleDisk'
     disk = Param.DiskImage("Disk Image")
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py
index 5d968cab0..193f31b0f 100644
--- a/src/python/m5/objects/SimpleOzoneCPU.py
+++ b/src/python/m5/objects/SimpleOzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
 from m5 import build_env
-from m5.config import *
 from BaseCPU import BaseCPU
 
 class SimpleOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 386f39277..bc2a002cb 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
 from m5 import build_env
-from m5.config import *
 
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
 
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 0b5ff9e7d..0b53153a0 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
 from Device import BasicPioDevice
 from Platform import Platform
 from AlphaConsole import AlphaConsole
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
index 8e1fd1a37..62062c6b1 100644
--- a/src/python/m5/objects/Uart.py
+++ b/src/python/m5/objects/Uart.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
 from m5 import build_env
-from m5.config import *
 from Device import BasicPioDevice
 
 class Uart(BasicPioDevice):
-- 
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