From ed22eb781dc7714c1b2ca17cf17824917e38319c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 7 Dec 2006 18:50:33 -0500 Subject: get legion/m5 to first tlb miss fault src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca --- src/python/m5/objects/T1000.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/python/m5/objects') diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index f4ec5bec4..79195d976 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -38,6 +38,22 @@ class T1000(Platform): ret_data64=0x0000000000000001, update_data=True, warn_access="Accessing L2 Cache Banks -- Unimplemented!") + fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, warn_access="Accessing SSI -- Unimplemented!") @@ -57,6 +73,10 @@ class T1000(Platform): self.fake_l2_2.pio = bus.port self.fake_l2_3.pio = bus.port self.fake_l2_4.pio = bus.port + self.fake_l2esr_1.pio = bus.port + self.fake_l2esr_2.pio = bus.port + self.fake_l2esr_3.pio = bus.port + self.fake_l2esr_4.pio = bus.port self.fake_ssi.pio = bus.port self.puart0.pio = bus.port self.hvuart.pio = bus.port -- cgit v1.2.3