From e04208f046237c74a2350d98a74a2fdc0ad838fa Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 08:37:55 -0700 Subject: Fix NextEthernetAddr. unproxy() needs to return a new object otherwise all instances will use the same value. This fix is more or less unique to NextEthernetAddr because its use of the proxy stuff is a bit different than everything else. --HG-- extra : convert_revision : 2ce452e37d00b9ba76b6abfaec0ad2e0073920d7 --- src/python/m5/params.py | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) (limited to 'src/python/m5') diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 9892df97c..da7ddd65e 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -51,6 +51,7 @@ import sys import time import convert +import proxy import ticks from util import * @@ -477,12 +478,13 @@ def IncEthernetAddr(addr, val = 1): assert(bytes[0] <= 255) return ':'.join(map(lambda x: '%02x' % x, bytes)) -class NextEthernetAddr(object): - addr = "00:90:00:00:00:01" +_NextEthernetAddr = "00:90:00:00:00:01" +def NextEthernetAddr(): + global _NextEthernetAddr - def __init__(self, inc = 1): - self.value = NextEthernetAddr.addr - NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc) + value = _NextEthernetAddr + _NextEthernetAddr = IncEthernetAddr(_NextEthernetAddr, 1) + return value class EthernetAddr(ParamValue): cxx_type = 'Net::EthAddr' @@ -508,17 +510,11 @@ class EthernetAddr(ParamValue): def unproxy(self, base): if self.value == NextEthernetAddr: - self.addr = self.value().value + return EthernetAddr(self.value()) return self - def __str__(self): - if self.value == NextEthernetAddr: - if hasattr(self, 'addr'): - return self.addr - else: - return "NextEthernetAddr (unresolved)" - else: - return self.value + def ini_str(self): + return self.value time_formats = [ "%a %b %d %H:%M:%S %Z %Y", "%a %b %d %H:%M:%S %Z %Y", @@ -1028,6 +1024,5 @@ __all__ = ['Param', 'VectorParam', # see comment on imports at end of __init__.py. from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass -import proxy import objects import internal -- cgit v1.2.3 From a575fbd4aaa45af90535f67d5100b95b3c610f93 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 21:20:04 -0700 Subject: Completely re-work how the scons framework incorporates swig and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. --HG-- extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb --- src/python/m5/internal/__init__.py | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 src/python/m5/internal/__init__.py (limited to 'src/python/m5') diff --git a/src/python/m5/internal/__init__.py b/src/python/m5/internal/__init__.py new file mode 100644 index 000000000..6b7859cd7 --- /dev/null +++ b/src/python/m5/internal/__init__.py @@ -0,0 +1,35 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import core +import debug +import event +import random +import sim_object +import stats +import trace -- cgit v1.2.3 From 0dfc29a023ff407846ea4f200547e2b2d9de9c1a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 7 May 2007 14:42:03 -0400 Subject: fix partial writes with a functional memory hack figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64 --- src/python/m5/objects/Bridge.py | 2 ++ src/python/m5/objects/Bus.py | 1 + 2 files changed, 3 insertions(+) (limited to 'src/python/m5') diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index ee8e76bff..e123c2891 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -9,3 +9,5 @@ class Bridge(MemObject): queue_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index 8226fe8d2..48dbbe307 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -11,6 +11,7 @@ class Bus(MemObject): clock = Param.Clock("1GHz", "bus clock speed") width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") if build_env['FULL_SYSTEM']: responder = BadAddr(pio_addr=0x0, pio_latency="1ps") default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") -- cgit v1.2.3 From 4a37c48e8e74405c39899e4914656930869f8bd4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:08:22 -0400 Subject: add/update parameters for bus bridge --HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91 --- src/python/m5/objects/Bridge.py | 7 +++++-- src/python/m5/objects/Device.py | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'src/python/m5') diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' -- cgit v1.2.3 From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- src/python/m5/objects/BaseCache.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/python/m5') diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") -- cgit v1.2.3 From 113319a7da9fe442f4f765b76c5728974824f2cc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:48:58 -0700 Subject: Float should have a c++ param type --HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673 --- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/python/m5') diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' -- cgit v1.2.3