From 31c8de306109f0fc3af6ad44aa474d86ba2f05f1 Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <andreas.sandberg@arm.com>
Date: Mon, 30 Jan 2017 12:00:21 +0000
Subject: python: Remove SWIG

Remove SWIG-specific Python code.

Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2922
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
---
 src/python/pybind11/pyobject.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/python/pybind11/pyobject.cc')

diff --git a/src/python/pybind11/pyobject.cc b/src/python/pybind11/pyobject.cc
index fe0ecba78..3b6f54982 100644
--- a/src/python/pybind11/pyobject.cc
+++ b/src/python/pybind11/pyobject.cc
@@ -80,7 +80,7 @@ lookupEthPort(SimObject *so, const std::string &name, int i)
 #endif
 
 /**
- * Connect the described MemObject ports.  Called from Python via SWIG.
+ * Connect the described MemObject ports.  Called from Python.
  * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports.
  * SimObject1 is the master, and SimObject2 is the slave
  */
-- 
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