From 0305159abf40765c6b8c506c777e3f62f3b6227e Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 19 May 2007 00:24:34 -0400 Subject: PhysicalMemory has vector of uniform ports instead of one special one. configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1 --- src/python/swig/pyobject.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/python/swig') diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index 11141fa84..2a5f2b9fb 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i) /** * Connect the described MemObject ports. Called from Python via SWIG. + * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. */ int connectPorts(SimObject *o1, const std::string &name1, int i1, -- cgit v1.2.3