From 2f145ac54ab3a9ed2c00e80460a10782da895604 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 16 Aug 2006 19:01:11 -0400 Subject: Fix Physical Memory to allow memory sizes bigger than 128MB. Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses causes a simulator segfault. src/SConscript: Add dram.cc to sconscript src/mem/physical.cc: src/mem/physical.hh: Add params struct to physical memory, use params, make latency function be virtual src/python/m5/objects/PhysicalMemory.py: Add DRAMMemory python class --HG-- extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d --- src/python/m5/objects/PhysicalMemory.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/python') diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index 9cc7510a2..f4818763f 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -7,3 +7,21 @@ class PhysicalMemory(MemObject): range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + -- cgit v1.2.3