From 4a37c48e8e74405c39899e4914656930869f8bd4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:08:22 -0400 Subject: add/update parameters for bus bridge --HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91 --- src/python/m5/objects/Bridge.py | 7 +++++-- src/python/m5/objects/Device.py | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'src/python') diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' -- cgit v1.2.3 From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- src/python/m5/objects/BaseCache.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/python') diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") -- cgit v1.2.3 From 113319a7da9fe442f4f765b76c5728974824f2cc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:48:58 -0700 Subject: Float should have a c++ param type --HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673 --- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/python') diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' -- cgit v1.2.3 From 011db5c8515804145202373440bad26fa21b30a7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 15:01:44 -0700 Subject: Move full CPU sim object stuff into the encumbered directory --HG-- extra : convert_revision : 788068dd4f4994d0016dba7e8705359d45a3a45c --- src/python/SConscript | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/python') diff --git a/src/python/SConscript b/src/python/SConscript index 3c5ab4da1..562278aa0 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -81,7 +81,6 @@ SimObject('m5/objects/Ethernet.py') SimObject('m5/objects/FUPool.py') SimObject('m5/objects/FastCPU.py') #SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FullCPU.py') SimObject('m5/objects/FuncUnit.py') SimObject('m5/objects/FuncUnitConfig.py') SimObject('m5/objects/FunctionalMemory.py') @@ -97,7 +96,6 @@ SimObject('m5/objects/O3CPU.py') SimObject('m5/objects/OzoneCPU.py') SimObject('m5/objects/Pci.py') SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/PipeTrace.py') SimObject('m5/objects/Platform.py') SimObject('m5/objects/Process.py') SimObject('m5/objects/Repl.py') -- cgit v1.2.3