From 8949d813ff6f9941faf1b173d408e13b0a2440a7 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Sun, 8 Oct 2006 01:12:42 -0400
Subject: Clean up configs.

configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
---
 src/python/m5/objects/FUPool.py         |  6 +++++
 src/python/m5/objects/FuncUnitConfig.py | 41 +++++++++++++++++++++++++++++++++
 src/python/m5/objects/O3CPU.py          | 11 +++++----
 3 files changed, 54 insertions(+), 4 deletions(-)
 create mode 100644 src/python/m5/objects/FuncUnitConfig.py

(limited to 'src/python')

diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index 4b4be79a6..916183bd7 100644
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,6 +1,12 @@
 from m5.SimObject import SimObject
 from m5.params import *
+from FuncUnit import *
+from FuncUnitConfig import *
 
 class FUPool(SimObject):
     type = 'FUPool'
     FUList = VectorParam.FUDesc("list of FU's for this pool")
+
+class DefaultFUPool(FUPool):
+    FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+               WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
new file mode 100644
index 000000000..43d7a4bb7
--- /dev/null
+++ b/src/python/m5/objects/FuncUnitConfig.py
@@ -0,0 +1,41 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+    opList = [ OpDesc(opClass='IntAlu') ]
+    count = 6
+
+class IntMultDiv(FUDesc):
+    opList = [ OpDesc(opClass='IntMult', opLat=3),
+               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+    count=2
+
+class FP_ALU(FUDesc):
+    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+               OpDesc(opClass='FloatCmp', opLat=2),
+               OpDesc(opClass='FloatCvt', opLat=2) ]
+    count = 4
+
+class FP_MultDiv(FUDesc):
+    opList = [ OpDesc(opClass='FloatMult', opLat=4),
+               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+    count = 2
+
+class ReadPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead') ]
+    count = 0
+
+class WritePort(FUDesc):
+    opList = [ OpDesc(opClass='MemWrite') ]
+    count = 0
+
+class RdWrPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+    count = 4
+
+class IprPort(FUDesc):
+    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+    count = 1
+
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 59b40c6e8..20eef383f 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -3,6 +3,7 @@ from m5.proxy import *
 from m5 import build_env
 from BaseCPU import BaseCPU
 from Checker import O3Checker
+from FUPool import *
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
@@ -14,11 +15,13 @@ class DerivO3CPU(BaseCPU):
     if build_env['USE_CHECKER']:
         if not build_env['FULL_SYSTEM']:
             checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
-                                              exitOnError=True,
+                                              exitOnError=False,
+                                              updateOnError=True,
                                               warnOnlyOnLoadError=False),
                                     "checker")
         else:
-            checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
+            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
+                                              warnOnlyOnLoadError=False), "checker")
             checker.itb = Parent.itb
             checker.dtb = Parent.dtb
 
@@ -57,7 +60,7 @@ class DerivO3CPU(BaseCPU):
     issueWidth = Param.Unsigned(8, "Issue width")
     wbWidth = Param.Unsigned(8, "Writeback width")
     wbDepth = Param.Unsigned(1, "Writeback depth")
-    fuPool = Param.FUPool("Functional Unit pool")
+    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
 
     iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
                "delay")
@@ -77,7 +80,7 @@ class DerivO3CPU(BaseCPU):
     localHistoryBits = Param.Unsigned(11, "Bits for the local history")
     globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
     globalCtrBits = Param.Unsigned(2, "Bits per counter")
-    globalHistoryBits = Param.Unsigned(4096, "Bits of history")
+    globalHistoryBits = Param.Unsigned(13, "Bits of history")
     choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
     choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
 
-- 
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