From baba18ab9214d1fe2236cd932c3bfca5ddfb06d6 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 16 Jun 2006 17:08:47 -0400 Subject: Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble. First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a --- src/python/m5/objects/AlphaFullCPU.py | 98 ----------------------------------- src/python/m5/objects/AlphaO3CPU.py | 98 +++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 98 deletions(-) delete mode 100644 src/python/m5/objects/AlphaFullCPU.py create mode 100644 src/python/m5/objects/AlphaO3CPU.py (limited to 'src/python') diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaFullCPU.py deleted file mode 100644 index 2988305d3..000000000 --- a/src/python/m5/objects/AlphaFullCPU.py +++ /dev/null @@ -1,98 +0,0 @@ -from m5 import build_env -from m5.config import * -from BaseCPU import BaseCPU - -class DerivAlphaFullCPU(BaseCPU): - type = 'DerivAlphaFullCPU' - activity = Param.Unsigned("Initial count") - numThreads = Param.Unsigned("number of HW thread contexts") - - checker = Param.BaseCPU(NULL, "checker") - - cachePorts = Param.Unsigned("Cache Ports") - - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - fuPool = Param.FUPool(NULL, "Functional Unit pool") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - trapLatency = Param.Tick("Trap latency") - fetchTrapLatency = Param.Tick("Fetch trap latency") - - predType = Param.String("Branch predictor type ('local', 'tournament')") - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numRobs = Param.Unsigned("Number of Reorder Buffers"); - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") - - smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") - smtFetchPolicy = Param.String("SMT Fetch policy") - smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") - smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") - smtIQPolicy = Param.String("SMT IQ Sharing Policy") - smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") - smtROBPolicy = Param.String("SMT ROB Sharing Policy") - smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") - smtCommitPolicy = Param.String("SMT Commit Policy") diff --git a/src/python/m5/objects/AlphaO3CPU.py b/src/python/m5/objects/AlphaO3CPU.py new file mode 100644 index 000000000..f14f8c88e --- /dev/null +++ b/src/python/m5/objects/AlphaO3CPU.py @@ -0,0 +1,98 @@ +from m5 import build_env +from m5.config import * +from BaseCPU import BaseCPU + +class DerivAlphaO3CPU(BaseCPU): + type = 'DerivAlphaO3CPU' + activity = Param.Unsigned("Initial count") + numThreads = Param.Unsigned("number of HW thread contexts") + + checker = Param.BaseCPU(NULL, "checker") + + cachePorts = Param.Unsigned("Cache Ports") + + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") + renameToFetchDelay = Param.Unsigned("Rename to fetch delay") + iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned("Commit to fetch delay") + fetchWidth = Param.Unsigned("Fetch width") + + renameToDecodeDelay = Param.Unsigned("Rename to decode delay") + iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned("Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") + decodeWidth = Param.Unsigned("Decode width") + + iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned("Commit to rename delay") + decodeToRenameDelay = Param.Unsigned("Decode to rename delay") + renameWidth = Param.Unsigned("Rename width") + + commitToIEWDelay = Param.Unsigned("Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned("Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + "to the IEW stage)") + issueWidth = Param.Unsigned("Issue width") + executeWidth = Param.Unsigned("Execute width") + executeIntWidth = Param.Unsigned("Integer execute width") + executeFloatWidth = Param.Unsigned("Floating point execute width") + executeBranchWidth = Param.Unsigned("Branch execute width") + executeMemoryWidth = Param.Unsigned("Memory execute width") + fuPool = Param.FUPool(NULL, "Functional Unit pool") + + iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") + commitWidth = Param.Unsigned("Commit width") + squashWidth = Param.Unsigned("Squash width") + trapLatency = Param.Tick("Trap latency") + fetchTrapLatency = Param.Tick("Fetch trap latency") + + predType = Param.String("Branch predictor type ('local', 'tournament')") + localPredictorSize = Param.Unsigned("Size of local predictor") + localCtrBits = Param.Unsigned("Bits per counter") + localHistoryTableSize = Param.Unsigned("Size of local history table") + localHistoryBits = Param.Unsigned("Bits for the local history") + globalPredictorSize = Param.Unsigned("Size of global predictor") + globalCtrBits = Param.Unsigned("Bits per counter") + globalHistoryBits = Param.Unsigned("Bits of history") + choicePredictorSize = Param.Unsigned("Size of choice predictor") + choiceCtrBits = Param.Unsigned("Bits of choice counters") + + BTBEntries = Param.Unsigned("Number of BTB entries") + BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") + + RASSize = Param.Unsigned("RAS size") + + LQEntries = Param.Unsigned("Number of load queue entries") + SQEntries = Param.Unsigned("Number of store queue entries") + LFSTSize = Param.Unsigned("Last fetched store table size") + SSITSize = Param.Unsigned("Store set ID table size") + + numRobs = Param.Unsigned("Number of Reorder Buffers"); + + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned("Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned("Number of instruction queue entries") + numROBEntries = Param.Unsigned("Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + + smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") + smtFetchPolicy = Param.String("SMT Fetch policy") + smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") + smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String("SMT IQ Sharing Policy") + smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String("SMT ROB Sharing Policy") + smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String("SMT Commit Policy") -- cgit v1.2.3 From 0bbd909f02e72a321a65b933104c5ef1e157116b Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 16 Jun 2006 17:52:15 -0400 Subject: Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. src/SConscript: Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree. src/cpu/o3/fu_pool.cc: Include the func unit file that's not in the encumbered directory. --HG-- extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241 --- src/python/m5/objects/FuncUnit.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 src/python/m5/objects/FuncUnit.py (limited to 'src/python') diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py new file mode 100644 index 000000000..f61590ae9 --- /dev/null +++ b/src/python/m5/objects/FuncUnit.py @@ -0,0 +1,17 @@ +from m5.config import * + +class OpType(Enum): + vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', + 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] + +class OpDesc(SimObject): + type = 'OpDesc' + issueLat = Param.Int(1, "cycles until another can be issued") + opClass = Param.OpType("type of operation") + opLat = Param.Int(1, "cycles until result is available") + +class FUDesc(SimObject): + type = 'FUDesc' + count = Param.Int("number of these FU's available") + opList = VectorParam.OpDesc("operation classes for this FU type") -- cgit v1.2.3 From e889b8242301b1123ffd4c05862f84826dd77806 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 16 Jun 2006 21:18:19 -0400 Subject: Add in some of the commonly used Trace/ExeTrace/Debug options. src/python/m5/__init__.py: Add in some of the commonly used Trace/ExeTrace/Debug options. Not terribly clean but it works. --HG-- extra : convert_revision : abb3cb4892512483a5031606baabf6540019233c --- src/python/m5/__init__.py | 93 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 83 insertions(+), 10 deletions(-) (limited to 'src/python') diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index f849a899b..c0728120c 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -67,15 +67,46 @@ def setTraceFlags(option, opt_str, value, parser): def setTraceStart(option, opt_str, value, parser): objects.Trace.start = value -def clearPCSymbol(option, opt_str, value, parser): - objects.ExecutionTrace.pc_symbol = False +def setTraceFile(option, opt_str, value, parser): + objects.Trace.file = value -def clearPrintCycle(option, opt_str, value, parser): - objects.ExecutionTrace.print_cycle = False +def usePCSymbol(option, opt_str, value, parser): + objects.ExecutionTrace.pc_symbol = value + +def printCycle(option, opt_str, value, parser): + objects.ExecutionTrace.print_cycle = value + +def printOp(option, opt_str, value, parser): + objects.ExecutionTrace.print_opclass = value + +def printThread(option, opt_str, value, parser): + objects.ExecutionTrace.print_thread = value + +def printEA(option, opt_str, value, parser): + objects.ExecutionTrace.print_effaddr = value + +def printData(option, opt_str, value, parser): + objects.ExecutionTrace.print_data = value + +def printFetchseq(option, opt_str, value, parser): + objects.ExecutionTrace.print_fetchseq = value + +def printCpseq(option, opt_str, value, parser): + objects.ExecutionTrace.print_cpseq = value + +def dumpOnExit(option, opt_str, value, parser): + objects.Trace.dump_on_exit = value + +def debugBreak(option, opt_str, value, parser): + objects.Debug.break_cycles = value def statsTextFile(option, opt_str, value, parser): objects.Statistics.text_file = value +# Extra list to help for options that are true or false +TrueOrFalse = ['True', 'False'] +TorF = "True | False" + # Standard optparse options. Need to be explicitly included by the # user script when it calls optparse.OptionParser(). standardOptions = [ @@ -83,12 +114,54 @@ standardOptions = [ callback=setTraceFlags), optparse.make_option("--tracestart", type="int", action="callback", callback=setTraceStart), - optparse.make_option("--nopcsymbol", action="callback", - callback=clearPCSymbol, - help="Turn off printing PC symbols in trace output"), - optparse.make_option("--noprintcycle", action="callback", - callback=clearPrintCycle, - help="Turn off printing cycles in trace output"), + optparse.make_option("--tracefile", type="string", action="callback", + callback=setTraceFile), + optparse.make_option("--pcsymbol", type="choice", choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=usePCSymbol, + help="Use PC symbols in trace output"), + optparse.make_option("--printcycle", type="choice", choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printCycle, + help="Print cycle numbers in trace output"), + optparse.make_option("--printopclass", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printOp, + help="Print cycle numbers in trace output"), + optparse.make_option("--printthread", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printThread, + help="Print thread number in trace output"), + optparse.make_option("--printeffaddr", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printEA, + help="Print effective address in trace output"), + optparse.make_option("--printdata", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printData, + help="Print result data in trace output"), + optparse.make_option("--printfetchseq", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printFetchseq, + help="Print fetch sequence numbers in trace output"), + optparse.make_option("--printcpseq", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=printCpseq, + help="Print correct path sequence numbers in trace output"), + optparse.make_option("--dumponexit", type="choice", + choices=TrueOrFalse, + default="True", metavar=TorF, + action="callback", callback=dumpOnExit, + help="Dump trace buffer on exit"), + optparse.make_option("--debugbreak", type="int", metavar="CYCLE", + action="callback", callback=debugBreak, + help="Cycle to create a breakpoint"), optparse.make_option("--statsfile", type="string", action="callback", callback=statsTextFile, metavar="FILE", help="Sets the output file for the statistics") -- cgit v1.2.3 From 4a9c0a7dfc8aa1fcd70ec2b194691adec9ce424e Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 17 Jun 2006 09:58:10 -0400 Subject: Add --outdir option. Didn't call it "-d" since that's already being used for "detailed cpu". Needed to add extra function for user script to pass parsed options back to m5 module. configs/test/fs.py: configs/test/test.py: Call setStandardOptions(). src/python/m5/__init__.py: Add --outdir option. Add setStandardOptions() so user script can pass parsed options back to m5 module. src/sim/main.cc: Add SWIG-wrappable function to set output dir. --HG-- extra : convert_revision : 1323bee69ca920c699a1cd1218e15b7b0875c1e5 --- src/python/m5/__init__.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/python') diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index c0728120c..19af24e6f 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -58,6 +58,20 @@ def AddToPath(path): sys.path.insert(1, path) +# The m5 module's pointer to the parsed options object +options = None + + +# User should call this function after calling parse_args() to pass +# parsed standard option values back into the m5 module for +# processing. +def setStandardOptions(_options): + # Set module global var + global options + options = _options + # tell C++ about output directory + main.setOutputDir(options.outdir) + # Callback to set trace flags. Not necessarily the best way to do # things in the long run (particularly if we change how these global # options are handled). @@ -110,6 +124,7 @@ TorF = "True | False" # Standard optparse options. Need to be explicitly included by the # user script when it calls optparse.OptionParser(). standardOptions = [ + optparse.make_option("--outdir", type="string", default="."), optparse.make_option("--traceflags", type="string", action="callback", callback=setTraceFlags), optparse.make_option("--tracestart", type="int", action="callback", @@ -187,7 +202,7 @@ def resolveSimObject(name): def instantiate(root): config.ticks_per_sec = float(root.clock.frequency) # ugly temporary hack to get output to config.ini - sys.stdout = file('config.ini', 'w') + sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w') root.print_ini() sys.stdout.close() # close config.ini sys.stdout = sys.__stdout__ # restore to original -- cgit v1.2.3 From d96d28e56d39eec0baa1377779119495cfbf4701 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 17 Jun 2006 12:08:19 -0400 Subject: Rename SWIG "main" module to "cc_main" so it's clear from the Python side that this is the interface to C++. src/SConscript: main_wrap.cc -> cc_main_wrap.cc src/python/SConscript: src/python/m5/__init__.py: src/sim/main.cc: s/main/cc_main/ src/python/m5/config.py: s/main/cc_main/ Also directly import cc_main so we don't need to put the "m5." in front all the time. --HG-- extra : convert_revision : 755552f70cf671881ff31e476c677b95ef12950d --- src/python/SConscript | 6 +++--- src/python/m5/__init__.py | 14 +++++++------- src/python/m5/config.py | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions(-) (limited to 'src/python') diff --git a/src/python/SConscript b/src/python/SConscript index 7b0f591eb..3a9def9a8 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -87,12 +87,12 @@ addPkg('m5') pyzip_files.append('m5/defines.py') pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) -env.Command(['swig/main_wrap.cc', 'm5/main.py'], - 'swig/main.i', +env.Command(['swig/cc_main_wrap.cc', 'm5/cc_main.py'], + 'swig/cc_main.i', '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES') -pyzip_dep_files.append('m5/main.py') +pyzip_dep_files.append('m5/cc_main.py') # Action function to build the zip archive. Uses the PyZipFile module # included in the standard Python library. diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 19af24e6f..ac6904277 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -30,11 +30,11 @@ import sys, os, time, atexit, optparse # import the SWIG-wrapped main C++ functions -import main +import cc_main # import a few SWIG-wrapped items (those that are likely to be used # directly by user scripts) completely into this module for # convenience -from main import simulate, SimLoopExitEvent +from cc_main import simulate, SimLoopExitEvent # import the m5 compile options import defines @@ -70,7 +70,7 @@ def setStandardOptions(_options): global options options = _options # tell C++ about output directory - main.setOutputDir(options.outdir) + cc_main.setOutputDir(options.outdir) # Callback to set trace flags. Not necessarily the best way to do # things in the long run (particularly if we change how these global @@ -206,10 +206,10 @@ def instantiate(root): root.print_ini() sys.stdout.close() # close config.ini sys.stdout = sys.__stdout__ # restore to original - main.loadIniFile(resolveSimObject) # load config.ini into C++ + cc_main.loadIniFile(resolveSimObject) # load config.ini into C++ root.createCCObject() root.connectPorts() - main.finalInit() + cc_main.finalInit() noDot = True # temporary until we fix dot if not noDot: dot = pydot.Dot() @@ -223,10 +223,10 @@ def instantiate(root): # Export curTick to user script. def curTick(): - return main.cvar.curTick + return cc_main.cvar.curTick # register our C++ exit callback function with Python -atexit.register(main.doExitCleanup) +atexit.register(cc_main.doExitCleanup) # This import allows user scripts to reference 'm5.objects.Foo' after # just doing an 'import m5' (without an 'import m5.objects'). May not diff --git a/src/python/m5/config.py b/src/python/m5/config.py index 058e72578..c29477465 100644 --- a/src/python/m5/config.py +++ b/src/python/m5/config.py @@ -30,7 +30,7 @@ import os, re, sys, types, inspect, copy import m5 -from m5 import panic +from m5 import panic, cc_main from convert import * from multidict import multidict @@ -529,7 +529,7 @@ class SimObject(object): def getCCObject(self): if not self._ccObject: self._ccObject = -1 # flag to catch cycles in recursion - self._ccObject = m5.main.createSimObject(self.path()) + self._ccObject = cc_main.createSimObject(self.path()) elif self._ccObject == -1: raise RuntimeError, "%s: recursive call to getCCObject()" \ % self.path() @@ -1443,7 +1443,7 @@ class PortRef(object): if self.ccConnected: # already done this return peer = self.peer - m5.main.connectPorts(self.simobj.getCCObject(), self.name, self.index, + cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index, peer.simobj.getCCObject(), peer.name, peer.index) self.ccConnected = True peer.ccConnected = True -- cgit v1.2.3