From 244e0c884c60c141ea1bc63bb93e0aee25d6a854 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Nov 2006 14:24:31 -0500 Subject: Remove hack by setting configuration better. src/dev/isa_fake.cc: src/dev/isa_fake.hh: No need for specialized init() function any more. src/python/m5/objects/Tsunami.py: Override responder when set by user. This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder. --HG-- extra : convert_revision : c547daf15b23a889c98e62bfd53c293c85d7a041 --- src/python/m5/objects/Tsunami.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/python') diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 78ab65b31..ffe93727b 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -76,6 +76,7 @@ class Tsunami(Platform): self.pchip.pio = bus.port self.pciconfig.pio = bus.default bus.responder_set = True + bus.responder = self.pciconfig self.fake_sm_chip.pio = bus.port self.fake_uart1.pio = bus.port self.fake_uart2.pio = bus.port -- cgit v1.2.3 From ea5df468820c1c152ecd6932ac6a2a67b3f1725d Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Nov 2006 15:45:03 -0500 Subject: Fix error message. --HG-- extra : convert_revision : 7ac0f40595c89b0d9352e82e447d25380b038408 --- src/python/m5/__init__.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/python') diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index d41fd5a61..42abfe2cc 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -171,10 +171,10 @@ def switchCpus(cpuList): for cpu in old_cpus: if not isinstance(cpu, objects.BaseCPU): - raise TypeError, "%s is not of type BaseCPU", cpu + raise TypeError, "%s is not of type BaseCPU" % cpu for cpu in new_cpus: if not isinstance(cpu, objects.BaseCPU): - raise TypeError, "%s is not of type BaseCPU", cpu + raise TypeError, "%s is not of type BaseCPU" % cpu # Drain all of the individual CPUs drain_event = cc_main.createCountedDrain() -- cgit v1.2.3 From f7a35c33d70d99c1276a70c2ed1a86719e64973b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 7 Nov 2006 15:51:37 -0500 Subject: add code to operate in lockstep with legion src/python/m5/main.py: add option to operate in lockstep with legion --HG-- extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628 --- src/python/m5/main.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/python') diff --git a/src/python/m5/main.py b/src/python/m5/main.py index ccd6c5807..ef37f62ac 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -181,6 +181,8 @@ bool_option("print-cpseq", default=False, help="Print correct path sequence numbers in trace output") #bool_option("print-reg-delta", default=False, # help="Print which registers changed to what in trace output") +bool_option("legion-lock", default=False, + help="Compare simulator state with Legion simulator every cycle") options = attrdict() arguments = [] @@ -296,6 +298,7 @@ def main(): objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq objects.ExecutionTrace.print_cpseq = options.print_cpseq #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta + objects.ExecutionTrace.legion_lockstep = options.legion_lock sys.argv = arguments sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path -- cgit v1.2.3 From 344f72dd62f6cc9ab8c7ab5454a320b2e5674a37 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 8 Nov 2006 13:04:36 -0500 Subject: Remove mem parameter. Should have been removed earlier. src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. --HG-- extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4 --- src/python/m5/objects/BaseCPU.py | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/python') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6dc08e46..4e34e8a4e 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -8,7 +8,6 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") @@ -47,7 +46,6 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] -# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) -- cgit v1.2.3 From 64c0d82dec8ae042d41b6dbaa17a40095bb09091 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 8 Nov 2006 15:05:23 -0500 Subject: simplify maxtick parsing in both the python and the c++. configs/common/Simulation.py: simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick. src/python/m5/__init__.py: make a new m5 param called MaxTick. src/sim/host.hh: fix the M5 def. of MaxTick src/sim/main.cc: Simplify the MaxTick/num_cycles parsing within main.cc --HG-- extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668 --- src/python/m5/__init__.py | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/python') diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 42abfe2cc..579562b38 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -39,6 +39,9 @@ from cc_main import simulate, SimLoopExitEvent # import the m5 compile options import defines +# define a MaxTick parameter +MaxTick = 2**63 - 1 + # define this here so we can use it right away if necessary def panic(string): print >>sys.stderr, 'panic:', string -- cgit v1.2.3