From 1f539f13c32ad5a9187d56a098d4c857639b0e05 Mon Sep 17 00:00:00 2001 From: Alexandru Dutu Date: Sun, 23 Nov 2014 18:01:09 -0800 Subject: mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. --- src/sim/Process.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/sim/Process.py') diff --git a/src/sim/Process.py b/src/sim/Process.py index f64ab0883..ca9aaf5b1 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -45,7 +45,7 @@ class Process(SimObject): @classmethod def export_methods(cls, code): - code('bool map(Addr vaddr, Addr paddr, int size);') + code('bool map(Addr vaddr, Addr paddr, int size, bool cacheable=true);') class EmulatedDriver(SimObject): type = 'EmulatedDriver' -- cgit v1.2.3