From d4273cc9a6f3c00566e97ebcd71509ed14477b37 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 18 Jul 2013 08:31:16 -0400 Subject: mem: Set the cache line size on a system level This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly. --- src/sim/System.py | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/sim/System.py') diff --git a/src/sim/System.py b/src/sim/System.py index 2cc171881..302e2fa60 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -63,6 +63,8 @@ class System(MemObject): # I/O bridge or cache mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory") + cache_line_size = Param.Unsigned(64, "Cache line size in bytes") + work_item_id = Param.Int(-1, "specific work item id") num_work_ids = Param.Int(16, "Number of distinct work item types") work_begin_cpu_id_exit = Param.Int(-1, -- cgit v1.2.3