From e78684fc6ce9dc127902ec3dada6bbd2f403ff12 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 19 Oct 2006 10:21:23 -0700 Subject: Add new event priority for trace enable events so that tracing gets turned on as the very first thing in the selected cycle (tick). --HG-- extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c --- src/sim/eventq.hh | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'src/sim/eventq.hh') diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 537bfb918..fa65b08af 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -120,10 +120,22 @@ class Event : public Serializable, public FastAlloc /// priority; these values are used to control events that need to /// be ordered within a cycle. enum Priority { - /// Breakpoints should happen before anything else, so we - /// don't miss any action when debugging. + /// If we enable tracing on a particular cycle, do that as the + /// very first thing so we don't miss any of the events on + /// that cycle (even if we enter the debugger). + Trace_Enable_Pri = -101, + + /// Breakpoints should happen before anything else (except + /// enabling trace output), so we don't miss any action when + /// debugging. Debug_Break_Pri = -100, + /// CPU switches schedule the new CPU's tick event for the + /// same cycle (after unscheduling the old CPU's tick event). + /// The switch needs to come before any tick events to make + /// sure we don't tick both CPUs in the same cycle. + CPU_Switch_Pri = -31, + /// For some reason "delayed" inter-cluster writebacks are /// scheduled before regular writebacks (which have default /// priority). Steve? @@ -132,12 +144,6 @@ class Event : public Serializable, public FastAlloc /// Default is zero for historical reasons. Default_Pri = 0, - /// CPU switches schedule the new CPU's tick event for the - /// same cycle (after unscheduling the old CPU's tick event). - /// The switch needs to come before any tick events to make - /// sure we don't tick both CPUs in the same cycle. - CPU_Switch_Pri = -31, - /// Serailization needs to occur before tick events also, so /// that a serialize/unserialize is identical to an on-line /// CPU switch. -- cgit v1.2.3