From db8c55dede65e07cb9ea8e95c48badd2ea24462f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 8 Jan 2018 04:41:25 -0800 Subject: x86, mem: Rewrite the multilevel page table class. The new version extracts all the x86 specific aspects of the class, and builds the interface around a variable collection of template arguments which are classes that represent the different levels of the page table. The multilevel page table class is now much more ISA independent. Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636 Reviewed-on: https://gem5-review.googlesource.com/7347 Reviewed-by: Brandon Potter Maintainer: Gabe Black --- src/sim/process.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/sim/process.cc') diff --git a/src/sim/process.cc b/src/sim/process.cc index 07c936e76..5e9c2b5e7 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -311,7 +311,7 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber) Addr paddr = system->allocPhysPages(npages); pTable->map(vaddr, paddr, size, clobber ? EmulationPageTable::Clobber : - EmulationPageTable::Zero); + EmulationPageTable::MappingFlags(0)); } void @@ -406,7 +406,7 @@ bool Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) { pTable->map(vaddr, paddr, size, - cacheable ? EmulationPageTable::Zero : + cacheable ? EmulationPageTable::MappingFlags(0) : EmulationPageTable::Uncacheable); return true; } -- cgit v1.2.3