From cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 13 Oct 2018 00:54:32 -0700 Subject: cpu: dev: sim: gpu-compute: Banish some ISA specific register types. These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/sim/syscall_emul.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/sim/syscall_emul.hh') diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index 91e115de0..3f06869aa 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -1275,8 +1275,8 @@ cloneFunc(SyscallDesc *desc, int callnum, Process *p, ThreadContext *tc) { int index = 0; - TheISA::IntReg flags = p->getSyscallArg(tc, index); - TheISA::IntReg newStack = p->getSyscallArg(tc, index); + RegVal flags = p->getSyscallArg(tc, index); + RegVal newStack = p->getSyscallArg(tc, index); Addr ptidPtr = p->getSyscallArg(tc, index); #if THE_ISA == RISCV_ISA or THE_ISA == ARM_ISA -- cgit v1.2.3