From 7846f59d0dcb36c13e06a3ba8a4c461e646582b6 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 3 Jun 2013 13:55:41 +0200 Subject: arch: Create a method to finalize physical addresses in the TLB Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations. --- src/sim/tlb.hh | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/sim/tlb.hh') diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index 95a252e16..f46c2d856 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -124,6 +124,23 @@ class GenericTLB : public BaseTLB Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); void translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); + + + /** + * Do post-translation physical address finalization. + * + * This method is used by some architectures that need + * post-translation massaging of physical addresses. For example, + * X86 uses this to remap physical addresses in the APIC range to + * a range of physical memory not normally available to real x86 + * implementations. + * + * @param req Request to updated in-place. + * @param tc Thread context that created the request. + * @param mode Request type (read/write/execute). + * @return A fault on failure, NoFault otherwise. + */ + Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; }; #endif // __ARCH_SPARC_TLB_HH__ -- cgit v1.2.3