From 8dd7700482b8ad7fa5e96469b23f0c917f5e3599 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 28 Jul 2007 20:30:43 -0700 Subject: Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7 --- src/sim/InstTracer.py | 35 ++++++++++++ src/sim/SConscript | 1 + src/sim/insttracer.hh | 146 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 src/sim/InstTracer.py create mode 100644 src/sim/insttracer.hh (limited to 'src/sim') diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py new file mode 100644 index 000000000..f7500f1e8 --- /dev/null +++ b/src/sim/InstTracer.py @@ -0,0 +1,35 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject +from m5.params import * + +class InstTracer(SimObject): + type = 'InstTracer' + cxx_namespace = 'Trace' + abstract = True diff --git a/src/sim/SConscript b/src/sim/SConscript index 455e5678a..6bd53e205 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -32,6 +32,7 @@ Import('*') SimObject('Root.py') SimObject('System.py') +SimObject('InstTracer.py') Source('async.cc') Source('core.cc') diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh new file mode 100644 index 000000000..ebeae1fe9 --- /dev/null +++ b/src/sim/insttracer.hh @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Steve Reinhardt + * Nathan Binkert + */ + +#ifndef __INSTRECORD_HH__ +#define __INSTRECORD_HH__ + +#include "base/trace.hh" +#include "cpu/inst_seq.hh" // for InstSeqNum +#include "cpu/static_inst.hh" +#include "sim/host.hh" +#include "sim/sim_object.hh" + +class ThreadContext; + +namespace Trace { + +class InstRecord +{ + protected: + Tick when; + + // The following fields are initialized by the constructor and + // thus guaranteed to be valid. + ThreadContext *thread; + // need to make this ref-counted so it doesn't go away before we + // dump the record + StaticInstPtr staticInst; + Addr PC; + bool misspeculating; + + // The remaining fields are only valid for particular instruction + // types (e.g, addresses for memory ops) or when particular + // options are enabled (e.g., tracing full register contents). + // Each data field has an associated valid flag to indicate + // whether the data field is valid. + Addr addr; + bool addr_valid; + + union { + uint64_t as_int; + double as_double; + } data; + enum { + DataInvalid = 0, + DataInt8 = 1, // set to equal number of bytes + DataInt16 = 2, + DataInt32 = 4, + DataInt64 = 8, + DataDouble = 3 + } data_status; + + InstSeqNum fetch_seq; + bool fetch_seq_valid; + + InstSeqNum cp_seq; + bool cp_seq_valid; + + public: + InstRecord(Tick _when, ThreadContext *_thread, + const StaticInstPtr &_staticInst, + Addr _pc, bool spec) + : when(_when), thread(_thread), + staticInst(_staticInst), PC(_pc), + misspeculating(spec) + { + data_status = DataInvalid; + addr_valid = false; + + fetch_seq_valid = false; + cp_seq_valid = false; + } + + virtual ~InstRecord() { } + + void setAddr(Addr a) { addr = a; addr_valid = true; } + + void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } + void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } + void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } + void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } + void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } + void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } + + void setData(int64_t d) { setData((uint64_t)d); } + void setData(int32_t d) { setData((uint32_t)d); } + void setData(int16_t d) { setData((uint16_t)d); } + void setData(int8_t d) { setData((uint8_t)d); } + + void setData(double d) { data.as_double = d; data_status = DataDouble; } + + void setFetchSeq(InstSeqNum seq) + { fetch_seq = seq; fetch_seq_valid = true; } + + void setCPSeq(InstSeqNum seq) + { cp_seq = seq; cp_seq_valid = true; } + + virtual void dump() = 0; +}; + +class InstTracer : public SimObject +{ + public: + InstTracer(const std::string & name) : SimObject(name) + {} + + virtual ~InstTracer() + {}; + + virtual InstRecord * + getInstRecord(Tick when, ThreadContext *tc, + const StaticInstPtr staticInst, Addr pc) = 0; +}; + + + +}; // namespace Trace + +#endif // __INSTRECORD_HH__ -- cgit v1.2.3 From 5e34c62b3b3f54c826730841029a875607824c42 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 29 Jul 2007 01:33:06 -0700 Subject: X86: Initial stack frame fixes and constant shuffling. The initial stack frame for x86 is now substantially more correct. The fixes made here can be back ported to SPARC and possible the other ISAs as well. The auxiliary vector types were moved to the LiveProcess base class because they are independent of ISA. Some of the types may only apply to Linux, though, so they may have to be moved. --HG-- extra : convert_revision : 89ace35fcc8eb9586d2fee8eeccbc3686499ef24 --- src/sim/process.hh | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'src/sim') diff --git a/src/sim/process.hh b/src/sim/process.hh index fa46b9c95..8c702da60 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -214,6 +214,32 @@ class LiveProcess : public Process public: + enum AuxiliaryVectorType { + M5_AT_NULL = 0, + M5_AT_IGNORE = 1, + M5_AT_EXECFD = 2, + M5_AT_PHDR = 3, + M5_AT_PHENT = 4, + M5_AT_PHNUM = 5, + M5_AT_PAGESZ = 6, + M5_AT_BASE = 7, + M5_AT_FLAGS = 8, + M5_AT_ENTRY = 9, + M5_AT_NOTELF = 10, + M5_AT_UID = 11, + M5_AT_EUID = 12, + M5_AT_GID = 13, + M5_AT_EGID = 14, + // The following may be specific to Linux + M5_AT_PLATFORM = 15, + M5_AT_HWCAP = 16, + M5_AT_CLKTCK = 17, + + M5_AT_SECURE = 23, + + M5_AT_VECTOR_SIZE = 44 + }; + inline uint64_t uid() {return __uid;} inline uint64_t euid() {return __euid;} inline uint64_t gid() {return __gid;} -- cgit v1.2.3