From e51b075a2706180bdc262cbcbdd5bafe5896ba12 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 17 Oct 2006 19:38:36 -0400 Subject: add code to serialize se structures. Lisa is working on the python side of things and will test src/mem/page_table.cc: src/mem/page_table.hh: add code to serialize/unserialize page table src/sim/process.cc: src/sim/process.hh: add code to serialize/unserialize process --HG-- extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e --- src/sim/process.cc | 35 +++++++++++++++++++++++++++++++++++ src/sim/process.hh | 3 +++ 2 files changed, 38 insertions(+) (limited to 'src/sim') diff --git a/src/sim/process.cc b/src/sim/process.cc index 46ccd2596..f3e289d41 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -240,6 +240,41 @@ Process::sim_fd(int tgt_fd) return fd_map[tgt_fd]; } +void +Process::serialize(std::ostream &os) +{ + SERIALIZE_SCALAR(initialContextLoaded); + SERIALIZE_SCALAR(brk_point); + SERIALIZE_SCALAR(stack_base); + SERIALIZE_SCALAR(stack_size); + SERIALIZE_SCALAR(stack_min); + SERIALIZE_SCALAR(next_thread_stack_base); + SERIALIZE_SCALAR(mmap_start); + SERIALIZE_SCALAR(mmap_end); + SERIALIZE_SCALAR(nxm_start); + SERIALIZE_SCALAR(nxm_end); + SERIALIZE_ARRAY(fd_map, MAX_FD); + + pTable->serialize(os); +} + +void +Process::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(initialContextLoaded); + UNSERIALIZE_SCALAR(brk_point); + UNSERIALIZE_SCALAR(stack_base); + UNSERIALIZE_SCALAR(stack_size); + UNSERIALIZE_SCALAR(stack_min); + UNSERIALIZE_SCALAR(next_thread_stack_base); + UNSERIALIZE_SCALAR(mmap_start); + UNSERIALIZE_SCALAR(mmap_end); + UNSERIALIZE_SCALAR(nxm_start); + UNSERIALIZE_SCALAR(nxm_end); + UNSERIALIZE_ARRAY(fd_map, MAX_FD); + + pTable->unserialize(cp, section); +} // diff --git a/src/sim/process.hh b/src/sim/process.hh index b2777170f..5c37f725e 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -162,6 +162,9 @@ class Process : public SimObject int sim_fd(int tgt_fd); virtual void syscall(int64_t callnum, ThreadContext *tc) = 0; + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; // -- cgit v1.2.3 From e78684fc6ce9dc127902ec3dada6bbd2f403ff12 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 19 Oct 2006 10:21:23 -0700 Subject: Add new event priority for trace enable events so that tracing gets turned on as the very first thing in the selected cycle (tick). --HG-- extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c --- src/sim/eventq.hh | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'src/sim') diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 537bfb918..fa65b08af 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -120,10 +120,22 @@ class Event : public Serializable, public FastAlloc /// priority; these values are used to control events that need to /// be ordered within a cycle. enum Priority { - /// Breakpoints should happen before anything else, so we - /// don't miss any action when debugging. + /// If we enable tracing on a particular cycle, do that as the + /// very first thing so we don't miss any of the events on + /// that cycle (even if we enter the debugger). + Trace_Enable_Pri = -101, + + /// Breakpoints should happen before anything else (except + /// enabling trace output), so we don't miss any action when + /// debugging. Debug_Break_Pri = -100, + /// CPU switches schedule the new CPU's tick event for the + /// same cycle (after unscheduling the old CPU's tick event). + /// The switch needs to come before any tick events to make + /// sure we don't tick both CPUs in the same cycle. + CPU_Switch_Pri = -31, + /// For some reason "delayed" inter-cluster writebacks are /// scheduled before regular writebacks (which have default /// priority). Steve? @@ -132,12 +144,6 @@ class Event : public Serializable, public FastAlloc /// Default is zero for historical reasons. Default_Pri = 0, - /// CPU switches schedule the new CPU's tick event for the - /// same cycle (after unscheduling the old CPU's tick event). - /// The switch needs to come before any tick events to make - /// sure we don't tick both CPUs in the same cycle. - CPU_Switch_Pri = -31, - /// Serailization needs to occur before tick events also, so /// that a serialize/unserialize is identical to an on-line /// CPU switch. -- cgit v1.2.3 From 6c6b78126a38cf92eef89f027312e1c7a063bd18 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 20 Oct 2006 11:37:59 -0700 Subject: Construct a correct value of PYTHONHOME from the interpreter running SCons, make it into a sticky option that can be overridden at build time, and set it up before the interpreter is started. Also, fix the code that turns sticky options into config/*.hh so that it works with types other than bool. --HG-- extra : convert_revision : 602398b35d4da4e813f78865678ed348fdea7270 --- src/sim/main.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/sim') diff --git a/src/sim/main.cc b/src/sim/main.cc index 8bb0d7aaa..133141e57 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -55,6 +55,7 @@ #include "base/statistics.hh" #include "base/str.hh" #include "base/time.hh" +#include "config/pythonhome.hh" #include "cpu/base.hh" #include "cpu/smt.hh" #include "mem/mem_object.hh" @@ -145,6 +146,11 @@ main(int argc, char **argv) if (setenv("PYTHONPATH", pythonpath.c_str(), true) == -1) fatal("setenv: %s\n", strerror(errno)); + char *python_home = getenv("PYTHONHOME"); + if (!python_home) + python_home = PYTHONHOME; + Py_SetPythonHome(python_home); + // initialize embedded Python interpreter Py_Initialize(); PySys_SetArgv(argc, argv); -- cgit v1.2.3