From 372adea6879ac549df4a415b5913d28b6683d535 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Thu, 4 Jan 2018 01:22:49 -0800
Subject: arch, mem, sim: Consolidate and rename the SE mode page table
 classes.

Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.

Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.

Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
---
 src/sim/process.cc | 8 +++++---
 src/sim/process.hh | 6 +++---
 2 files changed, 8 insertions(+), 6 deletions(-)

(limited to 'src/sim')

diff --git a/src/sim/process.cc b/src/sim/process.cc
index 77d7903a7..07c936e76 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -101,7 +101,7 @@
 using namespace std;
 using namespace TheISA;
 
-Process::Process(ProcessParams *params, PageTableBase *pTable,
+Process::Process(ProcessParams *params, EmulationPageTable *pTable,
                  ObjectFile *obj_file)
     : SimObject(params), system(params->system),
       useArchPT(params->useArchPT),
@@ -310,7 +310,8 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
     int npages = divCeil(size, (int64_t)PageBytes);
     Addr paddr = system->allocPhysPages(npages);
     pTable->map(vaddr, paddr, size,
-                clobber ? PageTableBase::Clobber : PageTableBase::Zero);
+                clobber ? EmulationPageTable::Clobber :
+                          EmulationPageTable::Zero);
 }
 
 void
@@ -405,7 +406,8 @@ bool
 Process::map(Addr vaddr, Addr paddr, int size, bool cacheable)
 {
     pTable->map(vaddr, paddr, size,
-                cacheable ? PageTableBase::Zero : PageTableBase::Uncacheable);
+                cacheable ? EmulationPageTable::Zero :
+                            EmulationPageTable::Uncacheable);
     return true;
 }
 
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 6d465aca9..cb2a3e2be 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -54,7 +54,7 @@ struct ProcessParams;
 
 class EmulatedDriver;
 class ObjectFile;
-class PageTableBase;
+class EmulationPageTable;
 class SyscallDesc;
 class SyscallReturn;
 class System;
@@ -63,7 +63,7 @@ class ThreadContext;
 class Process : public SimObject
 {
   public:
-    Process(ProcessParams *params, PageTableBase *pTable,
+    Process(ProcessParams *params, EmulationPageTable *pTable,
             ObjectFile *obj_file);
 
     void serialize(CheckpointOut &cp) const override;
@@ -176,7 +176,7 @@ class Process : public SimObject
     bool useArchPT; // flag for using architecture specific page table
     bool kvmInSE;   // running KVM requires special initialization
 
-    PageTableBase* pTable;
+    EmulationPageTable *pTable;
 
     SETranslatingPortProxy initVirtMem; // memory proxy for initial image load
 
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