From 649c239ceef2d107fae253b1008c6f214f242d73 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 13 Sep 2011 12:58:08 -0400 Subject: LSQ: Only trigger a memory violation with a load/load if the value changes. Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%). --- src/sim/faults.cc | 6 ++++++ src/sim/faults.hh | 10 ++++++++++ 2 files changed, 16 insertions(+) (limited to 'src/sim') diff --git a/src/sim/faults.cc b/src/sim/faults.cc index 3f1369bcc..bd05df834 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -56,6 +56,12 @@ void UnimpFault::invoke(ThreadContext * tc, StaticInstPtr inst) panic("Unimpfault: %s\n", panicStr.c_str()); } +void ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) +{ + tc->pcState(tc->pcState()); +} + + #if !FULL_SYSTEM void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst) { diff --git a/src/sim/faults.hh b/src/sim/faults.hh index 7f431b313..f5e9aded1 100644 --- a/src/sim/faults.hh +++ b/src/sim/faults.hh @@ -75,6 +75,16 @@ class UnimpFault : public FaultBase StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; +class ReExec : public FaultBase +{ + public: + virtual FaultName name() const { return "Re-execution fault";} + ReExec() {} + void invoke(ThreadContext *tc, + StaticInstPtr inst = StaticInst::nullStaticInstPtr); +}; + + #if !FULL_SYSTEM class GenericPageTableFault : public FaultBase { -- cgit v1.2.3