From 85940fd53795bd4b7b2118f4fa2a59a03bf6a8b1 Mon Sep 17 00:00:00 2001 From: Geoffrey Blake Date: Fri, 9 May 2014 18:58:47 -0400 Subject: arch, arm: Preserve TLB bootUncacheability when switching CPUs The ARM TLBs have a bootUncacheability flag used to make some loads and stores become uncacheable when booting in FS mode. Later the flag is cleared to let those loads and stores operate as normal. When doing a takeOverFrom(), this flag's state is not preserved and is momentarily reset until the CPSR is touched. On single core runs this is a non-issue. On multi-core runs this can lead to crashes on the O3 CPU model from the following series of events: 1) takeOverFrom executed to switch from Atomic -> O3 2) All bootUncacheability flags are reset to true 3) Core2 tries to execute a load covered by bootUncacheability, it is flagged as uncacheable 4) Core2's load needs to replay due to a pipeline flush 3) Core1 core does an action on CPSR 4) The handling code for CPSR then checks all other cores to determine if bootUncacheability can be set to false 5) Asynchronously set bootUncacheability on all cores to false 6) Core2 replays load previously set as uncacheable and notices it is now flagged as cacheable, leads to a panic. This patch implements takeOverFrom() functionality for the ARM TLBs to preserve flag values when switching from atomic -> detailed. --- src/sim/tlb.hh | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/sim') diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index f46c2d856..397d6e0f2 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -69,6 +69,11 @@ class BaseTLB : public SimObject */ virtual void flushAll() = 0; + /** + * Take over from an old tlb context + */ + virtual void takeOverFrom(BaseTLB *otlb) = 0; + /** * Get the table walker master port if present. This is used for * migrating port connections during a CPU takeOverFrom() -- cgit v1.2.3