From 16fa8d7cc8c92f5ab879e4cf9c6c0bbb3567860f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 24 May 2018 01:37:55 -0700 Subject: systemc: Import tests from the Accellera systemc distribution. Change-Id: Iad76b398949a55d768a34d027a2d8e3739953da6 Reviewed-on: https://gem5-review.googlesource.com/10845 Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black --- src/systemc/tests/systemc/misc/examples/README | 13 + .../tests/systemc/misc/examples/a2901/a2901.cpp | 81 + .../tests/systemc/misc/examples/a2901/a2901.f | 6 + .../tests/systemc/misc/examples/a2901/a2901.h | 105 + .../systemc/misc/examples/a2901/a2901_alu.cpp | 88 + .../tests/systemc/misc/examples/a2901/a2901_alu.h | 111 + .../misc/examples/a2901/a2901_alu_inputs.cpp | 79 + .../systemc/misc/examples/a2901/a2901_alu_inputs.h | 95 + .../systemc/misc/examples/a2901/a2901_edge.cpp | 81 + .../tests/systemc/misc/examples/a2901/a2901_edge.h | 102 + .../examples/a2901/a2901_output_and_shifter.cpp | 64 + .../misc/examples/a2901/a2901_output_and_shifter.h | 96 + .../systemc/misc/examples/a2901/a2901_test.cpp | 472 +++ .../tests/systemc/misc/examples/a2901/a2901_test.h | 146 + .../tests/systemc/misc/examples/a2901/common.h | 53 + .../systemc/misc/examples/a2901/golden/a2901.log | 2 + .../misc/examples/datawidth_int_c/datawidth.h | 77 + .../examples/datawidth_int_c/datawidth_int.cpp | 128 + .../datawidth_int_c/golden/datawidth_int.log | 4099 ++++++++++++++++++++ .../misc/examples/datawidth_int_c/stimgen.h | 77 + .../misc/examples/datawidth_int_file/datawidth.cpp | 65 + .../misc/examples/datawidth_int_file/datawidth.h | 77 + .../examples/datawidth_int_file/datawidth_int.f | 3 + .../datawidth_int_file/golden/datawidth_int.log | 4099 ++++++++++++++++++++ .../misc/examples/datawidth_int_file/main.cpp | 71 + .../misc/examples/datawidth_int_file/stimgen.cpp | 68 + .../misc/examples/datawidth_int_file/stimgen.h | 77 + .../tests/systemc/misc/examples/parsing/activa.cpp | 86 + .../misc/examples/parsing/golden/activa.log | 1 + 29 files changed, 10522 insertions(+) create mode 100644 src/systemc/tests/systemc/misc/examples/README create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901.f create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/common.h create mode 100644 src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth.h create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth_int.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_c/golden/datawidth_int.log create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_c/stimgen.h create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.h create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth_int.f create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/golden/datawidth_int.log create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/main.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.h create mode 100644 src/systemc/tests/systemc/misc/examples/parsing/activa.cpp create mode 100644 src/systemc/tests/systemc/misc/examples/parsing/golden/activa.log (limited to 'src/systemc/tests/systemc/misc/examples') diff --git a/src/systemc/tests/systemc/misc/examples/README b/src/systemc/tests/systemc/misc/examples/README new file mode 100644 index 000000000..b2148915a --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/README @@ -0,0 +1,13 @@ +Example Tests +------------- + +datawidth_int_c - This test consists of a single CC file. + The regression harness looks for the .cc + extension. + +datawidth_int_file - This test consists of multiple CC files + referenced by a single file that lists the + names of each CC file in the design. The + regression harness will detect the list file + by looking for the .f extension. + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp new file mode 100644 index 000000000..3ed026600 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.cpp @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901.h" +#include "a2901_test.h" + +SC_MODULE( twosome ) +{ + // signals + sig4 Y; + sig1 t_RAM0, t_RAM3, t_Q0, t_Q3, C4; + sig1 Gbar, Pbar, OVR, F3, F30; + sig9 I; + sig4 Aadd, Badd, D; + sig1 RAM0, RAM3, Q0, Q3, C0, OEbar; + + // modules + a2901 SLICE; + a2901_test TB; + + // constructor + twosome( sc_module_name, + const sc_clock& CLK_ ) + : SLICE( "a2901", + CLK_, + I, Aadd, Badd, D, RAM0, RAM3, Q0, Q3, C0, OEbar, + Y, t_RAM0, t_RAM3, t_Q0, t_Q3, C4, Gbar, Pbar, OVR, F3, F30 ), + TB( "a2901_test", + CLK_, + Y, t_RAM0, t_RAM3, t_Q0, t_Q3, C4, Gbar, Pbar, OVR, F3, F30, + I, Aadd, Badd, D, RAM0, RAM3, Q0, Q3, C0, OEbar ) + {} +}; + +int +sc_main( int, char*[] ) +{ + sc_clock clk; + + twosome AA( "AA", clk ); + + sc_start( 410000, SC_NS ); + + cout << sc_time_stamp() << endl; + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.f b/src/systemc/tests/systemc/misc/examples/a2901/a2901.f new file mode 100644 index 000000000..fa477be5e --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.f @@ -0,0 +1,6 @@ +a2901/a2901.cpp +a2901/a2901_alu.cpp +a2901/a2901_alu_inputs.cpp +a2901/a2901_edge.cpp +a2901/a2901_output_and_shifter.cpp +a2901/a2901_test.cpp diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901.h new file mode 100644 index 000000000..59c22a29c --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901.h @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_H +#define A2901_H + +#include "a2901_alu.h" +#include "a2901_alu_inputs.h" +#include "a2901_output_and_shifter.h" +#include "a2901_edge.h" + +SC_MODULE( a2901 ) +{ + // shared state + long RAM[15]; + + // signals + sig4 RE, S, F, Q, A; + sig5 R_ext, S_ext; + + // constructor + a2901( sc_module_name, + const sc_clock& CLK_, + const sig9& I_, + const sig4& Aadd_, + const sig4& Badd_, + const sig4& D_, + const sig1& RAM0_, + const sig1& RAM3_, + const sig1& Q0_, + const sig1& Q3_, + const sig1& C0_, + const sig1& OEbar_, + sig4& Y_, + sig1& t_RAM0_, + sig1& t_RAM3_, + sig1& t_Q0_, + sig1& t_Q3_, + sig1& C4_, + sig1& Gbar_, + sig1& Pbar_, + sig1& OVR_, + sig1& F3_, + sig1& F30_ ) + { + SC_NEW( a2901_alu( "alu", + I_, RE, S, C0_, + R_ext, S_ext, F, OVR_, C4_, Pbar_, Gbar_, + F3_, F30_ ) ); + SC_NEW( a2901_alu_inputs( "alu_inputs", + RAM, + I_, Aadd_, Badd_, D_, Q, + RE, S, A ) ); + SC_NEW( a2901_output_and_shifter( "o_and_s", + I_, OEbar_, A, F, Q, + Y_, t_RAM0_, t_RAM3_, + t_Q0_, t_Q3_ ) ); + SC_NEW( a2901_edge( "edge", + CLK_, + RAM, + I_, Badd_, F, Q3_, Q0_, RAM3_, RAM0_, + Q ) ); + // initialize the RAM (to get rid of UMRs) + for( int i = 0; i < 15; ++ i ) { + RAM[0] = 0; + } + } +}; + +#endif + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp new file mode 100644 index 000000000..b8862c63d --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.cpp @@ -0,0 +1,88 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_alu.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901_alu.h" + +void +a2901_alu::entry() +{ + int I53 = I.read().range(5,3); + + R_ext_v = (I53 == 0x1) ? sc_int<5> (0xf & ~(RE.read())) + : sc_int<5>( RE.read() ); + S_ext_v = (I53 == 0x2) ? sc_int<5> (0xf & ~(S.read()) ) + : sc_int<5>( S.read() ); + R_ext.write(R_ext_v); + S_ext.write(S_ext_v); + + switch (I53) { + case 0x0: + case 0x1: + case 0x2: + result = R_ext_v + S_ext_v + C0.read(); + break; + case 0x3: + result = R_ext_v | S_ext_v; + break; + case 0x4: + result = R_ext_v & S_ext_v; + break; + case 0x5: + result = ~(R_ext_v) & S_ext_v; + break; + case 0x6: + result = R_ext_v ^ S_ext_v; + break; + default: + result = ~(R_ext_v ^ S_ext_v); + } + + F.write(result); + OVR.write(!(R_ext_v[3] ^ S_ext_v[3]) & (R_ext_v[3] ^ result[3])); + //C4.write(result[4]); + C4.write((bool)result[4]); + temp_p = R_ext_v | S_ext_v; + temp_g = R_ext_v & S_ext_v; + Pbar.write((temp_p[0] & temp_p[1] & temp_p[2] & temp_p[3]) ? 0 : 1); + Gbar.write((temp_g[3] | + (temp_p[3] & temp_g[2]) | + (temp_p[3] & temp_p[2] & temp_g[1]) | + (temp_p[3] & temp_p[2] & temp_p[1] & temp_g[0])) ? 0 : 1); + //F3.write(result[3]); + F3.write((bool)result[3]); + F30.write((result[3] | result[2] | result[1] | result[0]) ? 0 : 1); +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h new file mode 100644 index 000000000..99bfbfcdd --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu.h @@ -0,0 +1,111 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_alu.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_ALU_H +#define A2901_ALU_H + +#include "common.h" + +SC_MODULE( a2901_alu ) +{ + SC_HAS_PROCESS( a2901_alu ); + + // inputs + const sig9& I; + const sig4& RE; + const sig4& S; + const sig1& C0; + + // outputs + sig5& R_ext; + sig5& S_ext; + sig4& F; + sig1& OVR; + sig1& C4; + sig1& Pbar; + sig1& Gbar; + sig1& F3; + sig1& F30; + + // temporaries + int5 result; + int5 R_ext_v; + int5 S_ext_v; + int5 temp_p; + int5 temp_g; + + // constructor + a2901_alu( sc_module_name, + const sig9& I_, + const sig4& RE_, + const sig4& S_, + const sig1& C0_, + sig5& R_ext_, + sig5& S_ext_, + sig4& F_, + sig1& OVR_, + sig1& C4_, + sig1& Pbar_, + sig1& Gbar_, + sig1& F3_, + sig1& F30_ ) + : I( I_ ), + RE( RE_ ), + S( S_ ), + C0( C0_ ), + R_ext( R_ext_ ), + S_ext( S_ext_ ), + F( F_ ), + OVR( OVR_ ), + C4( C4_ ), + Pbar( Pbar_ ), + Gbar( Gbar_ ), + F3( F3_ ), + F30( F30_ ) + { + SC_METHOD( entry ); + sensitive << I; + sensitive << RE; + sensitive << S; + sensitive << C0; + } + + void entry(); +}; + +#endif + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp new file mode 100644 index 000000000..90d37564e --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_alu_inputs.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901_alu_inputs.h" + +void +a2901_alu_inputs::entry() +{ + int4 Av; + int4 B; + + Av = RAM[Aadd.read()]; + B = RAM[Badd.read()]; + A.write(Av); + + switch((int)(I.read().range(2,0))) { + case 0x0: + case 0x1: + RE.write(Av); + break; + case 0x2: + case 0x3: + case 0x4: + RE.write(0x0); + break; + default: + RE.write(D.read()); + } + + switch((int)(I.read().range(2,0))) { + case 0x4: + case 0x5: + S.write(Av); + break; + case 0x1: + case 0x3: + S.write(B); + break; + case 0x7: + S.write(0x0); + break; + default: + S.write(Q.read()); + } +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h new file mode 100644 index 000000000..200c98020 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_alu_inputs.h @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_alu_inputs.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_ALU_INPUTS_H +#define A2901_ALU_INPUTS_H + +#include "common.h" + +SC_MODULE( a2901_alu_inputs ) +{ + SC_HAS_PROCESS( a2901_alu_inputs ); + + // shared state + long* RAM; + + // inputs + const sig9& I; + const sig4& Aadd; + const sig4& Badd; + const sig4& D; + const sig4& Q; + + // outputs + sig4& RE; + sig4& S; + sig4& A; + + // constructor + a2901_alu_inputs( sc_module_name, + long* RAM_, + const sig9& I_, + const sig4& Aadd_, + const sig4& Badd_, + const sig4& D_, + const sig4& Q_, + sig4& RE_, + sig4& S_, + sig4& A_ ) + : RAM( RAM_ ), + I( I_ ), + Aadd( Aadd_ ), + Badd( Badd_ ), + D( D_ ), + Q( Q_ ), + RE( RE_ ), + S( S_ ), + A( A_ ) + { + SC_METHOD( entry ); + sensitive << I; + sensitive << Aadd; + sensitive << Badd; + sensitive << D; + sensitive << Q; + } + + void entry(); +}; + +#endif + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp new file mode 100644 index 000000000..55be5e060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.cpp @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_edge.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901_edge.h" + + +void +a2901_edge::entry() +{ + i86 = I.read().range(8,6); + i87 = I.read().range(8,7); + q31 = Q.read().range(3,1); + q20 = Q.read().range(2,0); + f31 = F.read().range(3,1); + + switch ((int)i87) { + case 0: + RAM[Badd.read()] = RAM[Badd.read()]; + break; + case 1: + RAM[Badd.read()] = F.read(); + break; + case 2: + RAM[Badd.read()] = (RAM3.read(),f31); + break; + case 3: + RAM[Badd.read()] = (f20, RAM0.read()); + break; + } + +#if SUN_HAS_FIXED_THIS_BUG_IN_SC62 + Q.write( (i86 == 0x0) ? F.read() : + (i86 == 0x4) ? sc_uint<4>((Q3.read(),q31)) : + (i86 == 0x6) ? sc_uint<4>((q20,Q0.read())) : + Q.read()); +#else + if( i86 == 0x0 ) { + Q.write( F.read() ); + } else if( i86 == 0x4 ) { + Q.write( ( Q3.read(), q31 ) ); + } else if( i86 == 0x6 ) { + Q.write( ( q20, Q0.read() ) ); + } else { + Q.write( Q.read() ); + } +#endif +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h new file mode 100644 index 000000000..6af666fac --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_edge.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_edge.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_EDGE_H +#define A2901_EDGE_H + +#include "common.h" + +SC_MODULE( a2901_edge ) +{ + SC_HAS_PROCESS( a2901_edge ); + + // clock + const sc_clock& CLK; + + // shared state + long* RAM; + + // inputs + const sig9& I; + const sig4& Badd; + const sig4& F; + const sig1& Q3; + const sig1& Q0; + const sig1& RAM3; + const sig1& RAM0; + + // outputs + sig4& Q; + + // temporaries + sc_uint<3> i86; + sc_uint<3> i87; + sc_uint<3> q31, q20; + sc_uint<3> f31, f20; + + // constructor + a2901_edge( sc_module_name, + const sc_clock& CLK_, + long* RAM_, + const sig9& I_, + const sig4& Badd_, + const sig4& F_, + const sig1& Q3_, + const sig1& Q0_, + const sig1& RAM3_, + const sig1& RAM0_, + sig4& Q_ ) + : CLK( CLK_ ), + RAM( RAM_ ), + I( I_ ), + Badd( Badd_ ), + F( F_ ), + Q3( Q3_ ), + Q0( Q0_ ), + RAM3( RAM3_ ), + RAM0( RAM0_ ), + Q( Q_ ) + { + SC_METHOD( entry ); + sensitive << CLK.posedge_event(); + } + + void entry(); +}; + +#endif + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp new file mode 100644 index 000000000..92229c4ec --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.cpp @@ -0,0 +1,64 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_output_and_shifter.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901_output_and_shifter.h" + +void +a2901_output_and_shifter::entry() +{ + bool i8, i7, f0, f3, q0, q3; + sc_uint<3> i86; + int4 z4; + + z4 = 0x0; + i86 = I.read().range(8,6); + i8 = I.read()[8]; + i7 = I.read()[7]; + f0 = F.read()[0]; + f3 = F.read()[3]; + q0 = Q.read()[0]; + q3 = Q.read()[3]; + + Y.write( ( ( i86 == 0x2 ) && ( OEbar.read() == 0x0)) ? (uint64)A.read() : + (!( i86 == 0x2 ) && ( OEbar.read() == 0x0)) ? + (uint64)F.read() : (uint64)z4); + + t_RAM0 .write( (( i8 == 0x1) && ( i7 == 0x0 )) ? f0 : 0x0); + t_RAM3 .write( (( i8 == 0x1) && ( i7 == 0x1 )) ? f3 : 0x0); + t_Q3 .write( (( i8 == 0x1) && ( i7 == 0x1)) ? q3 : 0x0); + t_Q0 .write( (( i8 == 0x1) && ( i7 == 0x0)) ? q0 : 0x0); +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h new file mode 100644 index 000000000..63eb7513a --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_output_and_shifter.h @@ -0,0 +1,96 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_output_and_shifter.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_OUTPUT_AND_SHIFTER_H +#define A2901_OUTPUT_AND_SHIFTER_H + +#include "common.h" + +SC_MODULE( a2901_output_and_shifter ) +{ + SC_HAS_PROCESS( a2901_output_and_shifter ); + + // inputs + const sig9& I; + const sig1& OEbar; + const sig4& A; + const sig4& F; + const sig4& Q; + + // outputs + sig4& Y; + sig1& t_RAM0; + sig1& t_RAM3; + sig1& t_Q0; + sig1& t_Q3; + + // constructor + a2901_output_and_shifter( sc_module_name, + const sig9& I_, + const sig1& OEbar_, + const sig4& A_, + const sig4& F_, + const sig4& Q_, + sig4& Y_, + sig1& t_RAM0_, + sig1& t_RAM3_, + sig1& t_Q0_, + sig1& t_Q3_ ) + : I( I_ ), + OEbar( OEbar_ ), + A( A_ ), + F( F_ ), + Q( Q_ ), + Y( Y_ ), + t_RAM0( t_RAM0_ ), + t_RAM3( t_RAM3_ ), + t_Q0( t_Q0_ ), + t_Q3( t_Q3_ ) + { + SC_METHOD( entry ); + sensitive << I; + sensitive << OEbar; + sensitive << A; + sensitive << F; + sensitive << Q; + } + + void entry(); +}; + +#endif + diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp new file mode 100644 index 000000000..a2a66287f --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.cpp @@ -0,0 +1,472 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "a2901_test.h" + +void +a2901_test::entry() +{ + switch (vec_cnt++) { + case 0: + I. write(0x7); + D. write( 0); + C0. write( 0); + OEbar.write( 0); + break; + case 1: + I. write(0x46); + D. write( 0); + C0. write( 0); + OEbar.write( 0); + break; + case 2: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000 (%0d)\n", (int)Y.read()); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1 (%0d)\n", (int)F30.read()); + + I.write(0x7); + D.write(0x0); + C0.write(0x0); + OEbar.write(0x0); + + break; + case 3: + I.write(0x46); + D.write(0x0); + C0.write(0x1); + OEbar.write(0x0); + break; + case 4: + if (Y.read() != 0x1) fprintf(stderr,"Y != 4'b0001\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I.write(0x7); + D.write(0xf); // N("4'b1111") + C0.write(0x0); + OEbar.write(0x0); + + break; + case 5: + I.write(0x46); + D.write(0x0); + C0.write(0x0); + OEbar.write(0x0); + + break; + case 6: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I.write(0x7); + D.write(0xf); + C0.write(0x0); + OEbar.write(0x0); + + break; + case 7: + I.write(0x46); + D.write(0x0); + C0.write(0x1); + OEbar.write(0x0); + break; + case 8: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + I.write(0x7); + D.write(0xf); + C0.write(0x0); + OEbar.write(0x0); + break; + case 9: + I.write(0x46); + D.write(0xf); + C0.write(0x0); + OEbar.write(0x0); + break; + case 10: + if (Y.read() != 0xe) fprintf(stderr,"Y != 4'b1110\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I.write(0x7); + D.write(0xf); + C0.write(0x0); + OEbar.write(0x0); + break; + case 11: + I.write(0x46); + D.write(0xf); + C0.write(0x1); + OEbar.write(0x0); + break; + case 12: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 13: + I .write( 0x46); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 14: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 15: + I .write( 0x46); + D .write( 0xf); + C0 .write( 0x1); + OEbar .write( 0x0); + break; + case 16: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + I .write( 0x7); + D .write( 0x1); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 17: + I .write( 0x6); + D .write( 0x1); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 18: + if (Y.read() != 0x2) fprintf(stderr,"Y != 4'b0010\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x2); // N("4'b0010") + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 19: + I .write( 0x46); + D .write( 0x2); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 20: + if (Y.read() != 0x4) fprintf(stderr,"Y != 4'b0100\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x4); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 21: + I .write( 0x46); + D .write( 0x4); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 22: + if (Y.read() != 0x8) fprintf(stderr,"Y != 4'b1000\n"); + if (C4.read()!= 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x1) fprintf(stderr,"OVR != 1'b1\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x8); // N("4'b1000") + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 23: + I .write( 0x46); + D .write( 0x8); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 24: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x1) fprintf(stderr,"OVR != 1'b1\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + // ******** SUBTRACTION S - R ******** + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 25: + I .write( 0x4e); // N("9'b001001110") + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 26: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 27: + I .write( 0x4e); + D .write( 0x0); + C0 .write( 0x1); + OEbar .write( 0x0); + break; + case 28: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 29: + I .write( 0x4e); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 30: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + I .write( 0x7); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 31: + I .write( 0x4e); + D .write( 0xf); + C0 .write( 0x1); + OEbar .write( 0x0); + + break; + case 32: + if (Y.read() != 0x1) fprintf(stderr,"Y != 4'b0001\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x1) fprintf(stderr,"Pbar != 1'b1\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 33: + I .write( 0x4e); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 34: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x0) fprintf(stderr,"C4 != 1'b0\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 35: + I .write( 0x4e); + D .write( 0xf); + C0 .write( 0x1); + OEbar .write( 0x0); + + break; + case 36: + if (Y.read() != 0x0) fprintf(stderr,"Y != 4'b0000\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x1) fprintf(stderr,"Gbar != 1'b1\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x0) fprintf(stderr,"F3 != 1'b0\n"); + if (F30.read() != 0x1) fprintf(stderr,"F30 != 1'b1\n"); + + I .write( 0x7); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 37: + I .write( 0x4e); + D .write( 0x0); + C0 .write( 0x0); + OEbar .write( 0x0); + + break; + case 38: + if (Y.read() != 0xe) fprintf(stderr,"Y != 4'b1110\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0xf); + C0 .write( 0x0); + OEbar .write( 0x0); + break; + case 39: + I .write( 0x4e); + D .write( 0x0); + C0 .write( 0x1); + OEbar .write( 0x0); + break; + case 40: + if (Y.read() != 0xf) fprintf(stderr,"Y != 4'b1111\n"); + if (C4.read() != 0x1) fprintf(stderr,"C4 != 1'b1\n"); + if (Gbar.read() != 0x0) fprintf(stderr,"Gbar != 1'b0\n"); + if (Pbar.read() != 0x0) fprintf(stderr,"Pbar != 1'b0\n"); + if (OVR.read() != 0x0) fprintf(stderr,"OVR != 1'b0\n"); + if (F3.read() != 0x1) fprintf(stderr,"F3 != 1'b1\n"); + if (F30.read() != 0x0) fprintf(stderr,"F30 != 1'b0\n"); + + I .write( 0x7); + D .write( 0x0); // 0x1; + C0 .write( 0x0); + OEbar .write( 0x0); + + if (++loop < 100000) + vec_cnt = 0; + else { + printf ("loops = %d\n", loop); + sc_stop(); + } + break; + } +} diff --git a/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h new file mode 100644 index 000000000..e4edd755f --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/a2901_test.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + a2901_test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef A2901_TEST_H +#define A2901_TEST_H + +#include "common.h" + +SC_MODULE( a2901_test ) +{ + SC_HAS_PROCESS( a2901_test ); + + // clock + const sc_clock& CLK; + + // inputs + const sig4& Y; + const sig1& t_RAM0; + const sig1& t_RAM3; + const sig1& t_Q0; + const sig1& t_Q3; + const sig1& C4; + const sig1& Gbar; + const sig1& Pbar; + const sig1& OVR; + const sig1& F3; + const sig1& F30; + + // outputs + sig9& I; + sig4& Aadd; + sig4& Badd; + sig4& D; + sig1& RAM0; + sig1& RAM3; + sig1& Q0; + sig1& Q3; + sig1& C0; + sig1& OEbar; + + // temporaries + int vec_cnt; + int loop; + + // constructor + a2901_test( sc_module_name, + const sc_clock& CLK_, + const sig4& Y_, + const sig1& t_RAM0_, + const sig1& t_RAM3_, + const sig1& t_Q0_, + const sig1& t_Q3_, + const sig1& C4_, + const sig1& Gbar_, + const sig1& Pbar_, + const sig1& OVR_, + const sig1& F3_, + const sig1& F30_, + sig9& I_, + sig4& Aadd_, + sig4& Badd_, + sig4& D_, + sig1& RAM0_, + sig1& RAM3_, + sig1& Q0_, + sig1& Q3_, + sig1& C0_, + sig1& OEbar_ ) + : CLK( CLK_ ), + Y( Y_ ), + t_RAM0( t_RAM0_ ), + t_RAM3( t_RAM3_ ), + t_Q0( t_Q0_ ), + t_Q3( t_Q3_ ), + C4( C4_ ), + Gbar( Gbar_ ), + Pbar( Pbar_ ), + OVR( OVR_ ), + F3( F3_ ), + F30( F30_ ), + I( I_ ), + Aadd( Aadd_ ), + Badd( Badd_ ), + D( D_ ), + RAM0( RAM0_ ), + RAM3( RAM3_ ), + Q0( Q0_ ), + Q3( Q3_ ), + C0( C0_ ), + OEbar( OEbar_ ) + { + vec_cnt = 0; + loop = 0; + + // init + I.write( 0x7 ); + D.write( 0 ); + C0.write( 0 ); + OEbar.write( 0 ); + Aadd.write( 0 ); + Badd.write( 0 ); + Q0.write( 0 ); + Q3.write( 0 ); + + SC_METHOD( entry ); + sensitive << CLK.posedge_event(); + } + + void entry(); +}; + +#endif diff --git a/src/systemc/tests/systemc/misc/examples/a2901/common.h b/src/systemc/tests/systemc/misc/examples/a2901/common.h new file mode 100644 index 000000000..073976081 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/common.h @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef bool int1; +typedef sc_uint<4> int4; +typedef sc_uint<5> int5; +typedef sc_uint<9> int9; + +typedef sc_signal sig1; +typedef sc_signal sig4; +typedef sc_signal sig5; +typedef sc_signal sig9; + +#endif diff --git a/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log b/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log new file mode 100644 index 000000000..5667dbd19 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/a2901/golden/a2901.log @@ -0,0 +1,2 @@ +SystemC Simulation +410 us diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth.h b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth.h new file mode 100644 index 000000000..5be0bfed9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datawidth.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /**************************************/ + /* Interface Filename: datawidth.h */ + /**************************************/ + +#include "systemc.h" + +SC_MODULE( datawidth ) +{ + SC_HAS_PROCESS( datawidth ); + + sc_in_clk clk; + + // Inputs + const sc_signal& in1; + const sc_signal& in2; + const sc_signal& ready; + // Outputs + sc_signal& result; + + // Constructor + datawidth (sc_module_name NAME, + sc_clock& TICK, + const sc_signal& IN1, + const sc_signal& IN2, + const sc_signal& READY, + sc_signal& RESULT ) + + : + in1 (IN1), + in2 (IN2), + ready (READY), + result (RESULT) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth_int.cpp b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth_int.cpp new file mode 100644 index 000000000..3548a3ea8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/datawidth_int.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datawidth_int.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "datawidth.h" +#include "stimgen.h" + + /*******************************************/ + /* Implementation Filename: datawidth.cc */ + /*******************************************/ + +void +datawidth::entry() +{ + int tmp_a; + int tmp_b; + int tmp_result; + + while (true) { + + // HANDSHAKING + do { wait(); } while (ready == 0); + + // COMPUTATION + tmp_a = in1.read(); + tmp_b = in2.read(); + tmp_result = tmp_a + tmp_b; + + // WRITE OUTPUT + result.write(tmp_result); // result = in1 + in2 + wait(); + } +} + /*****************************************/ + /* Implementation Filename: stimgen.cc */ + /*****************************************/ + +void +stimgen::entry() +{ + int i; + int j; + + ready.write(0); + + for (i = 0; i < 64; i++) { // integer in1 (6 bits of data) + for (j = 0; j < 64; j++) { // integer in2 (6 bits of data) + in1.write(i); + in2.write(j); + ready.write(1); + wait(); + + ready.write(0); + wait(); + + cout << in1.read() << " + " << in2.read() + << " = " << result.read() << endl; + } + } + + sc_stop(); +} + + /***************************************/ + /* Main Filename: main.cc */ + /***************************************/ + /* */ + /* int = int + int */ + /* */ + /* Max addition is 63 + 63 */ + /* */ + /***************************************/ + +int +sc_main(int ac, char *av[]) +{ + +// Signal Instantiation + sc_signal in1 ("in1"); + sc_signal in2 ("in2"); + sc_signal result ("result"); + sc_signal ready ("ready"); + +// Clock Instantiation + sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS); + +// Process Instantiation + datawidth D1 ("D1", clk, in1, in2, ready, result); + + stimgen T1 ("T1", clk, result, in1, in2, ready); + +// Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_c/golden/datawidth_int.log b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/golden/datawidth_int.log new file mode 100644 index 000000000..b168b0482 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/golden/datawidth_int.log @@ -0,0 +1,4099 @@ +SystemC Simulation +0 + 0 = 0 +0 + 1 = 1 +0 + 2 = 2 +0 + 3 = 3 +0 + 4 = 4 +0 + 5 = 5 +0 + 6 = 6 +0 + 7 = 7 +0 + 8 = 8 +0 + 9 = 9 +0 + 10 = 10 +0 + 11 = 11 +0 + 12 = 12 +0 + 13 = 13 +0 + 14 = 14 +0 + 15 = 15 +0 + 16 = 16 +0 + 17 = 17 +0 + 18 = 18 +0 + 19 = 19 +0 + 20 = 20 +0 + 21 = 21 +0 + 22 = 22 +0 + 23 = 23 +0 + 24 = 24 +0 + 25 = 25 +0 + 26 = 26 +0 + 27 = 27 +0 + 28 = 28 +0 + 29 = 29 +0 + 30 = 30 +0 + 31 = 31 +0 + 32 = 32 +0 + 33 = 33 +0 + 34 = 34 +0 + 35 = 35 +0 + 36 = 36 +0 + 37 = 37 +0 + 38 = 38 +0 + 39 = 39 +0 + 40 = 40 +0 + 41 = 41 +0 + 42 = 42 +0 + 43 = 43 +0 + 44 = 44 +0 + 45 = 45 +0 + 46 = 46 +0 + 47 = 47 +0 + 48 = 48 +0 + 49 = 49 +0 + 50 = 50 +0 + 51 = 51 +0 + 52 = 52 +0 + 53 = 53 +0 + 54 = 54 +0 + 55 = 55 +0 + 56 = 56 +0 + 57 = 57 +0 + 58 = 58 +0 + 59 = 59 +0 + 60 = 60 +0 + 61 = 61 +0 + 62 = 62 +0 + 63 = 63 +1 + 0 = 1 +1 + 1 = 2 +1 + 2 = 3 +1 + 3 = 4 +1 + 4 = 5 +1 + 5 = 6 +1 + 6 = 7 +1 + 7 = 8 +1 + 8 = 9 +1 + 9 = 10 +1 + 10 = 11 +1 + 11 = 12 +1 + 12 = 13 +1 + 13 = 14 +1 + 14 = 15 +1 + 15 = 16 +1 + 16 = 17 +1 + 17 = 18 +1 + 18 = 19 +1 + 19 = 20 +1 + 20 = 21 +1 + 21 = 22 +1 + 22 = 23 +1 + 23 = 24 +1 + 24 = 25 +1 + 25 = 26 +1 + 26 = 27 +1 + 27 = 28 +1 + 28 = 29 +1 + 29 = 30 +1 + 30 = 31 +1 + 31 = 32 +1 + 32 = 33 +1 + 33 = 34 +1 + 34 = 35 +1 + 35 = 36 +1 + 36 = 37 +1 + 37 = 38 +1 + 38 = 39 +1 + 39 = 40 +1 + 40 = 41 +1 + 41 = 42 +1 + 42 = 43 +1 + 43 = 44 +1 + 44 = 45 +1 + 45 = 46 +1 + 46 = 47 +1 + 47 = 48 +1 + 48 = 49 +1 + 49 = 50 +1 + 50 = 51 +1 + 51 = 52 +1 + 52 = 53 +1 + 53 = 54 +1 + 54 = 55 +1 + 55 = 56 +1 + 56 = 57 +1 + 57 = 58 +1 + 58 = 59 +1 + 59 = 60 +1 + 60 = 61 +1 + 61 = 62 +1 + 62 = 63 +1 + 63 = 64 +2 + 0 = 2 +2 + 1 = 3 +2 + 2 = 4 +2 + 3 = 5 +2 + 4 = 6 +2 + 5 = 7 +2 + 6 = 8 +2 + 7 = 9 +2 + 8 = 10 +2 + 9 = 11 +2 + 10 = 12 +2 + 11 = 13 +2 + 12 = 14 +2 + 13 = 15 +2 + 14 = 16 +2 + 15 = 17 +2 + 16 = 18 +2 + 17 = 19 +2 + 18 = 20 +2 + 19 = 21 +2 + 20 = 22 +2 + 21 = 23 +2 + 22 = 24 +2 + 23 = 25 +2 + 24 = 26 +2 + 25 = 27 +2 + 26 = 28 +2 + 27 = 29 +2 + 28 = 30 +2 + 29 = 31 +2 + 30 = 32 +2 + 31 = 33 +2 + 32 = 34 +2 + 33 = 35 +2 + 34 = 36 +2 + 35 = 37 +2 + 36 = 38 +2 + 37 = 39 +2 + 38 = 40 +2 + 39 = 41 +2 + 40 = 42 +2 + 41 = 43 +2 + 42 = 44 +2 + 43 = 45 +2 + 44 = 46 +2 + 45 = 47 +2 + 46 = 48 +2 + 47 = 49 +2 + 48 = 50 +2 + 49 = 51 +2 + 50 = 52 +2 + 51 = 53 +2 + 52 = 54 +2 + 53 = 55 +2 + 54 = 56 +2 + 55 = 57 +2 + 56 = 58 +2 + 57 = 59 +2 + 58 = 60 +2 + 59 = 61 +2 + 60 = 62 +2 + 61 = 63 +2 + 62 = 64 +2 + 63 = 65 +3 + 0 = 3 +3 + 1 = 4 +3 + 2 = 5 +3 + 3 = 6 +3 + 4 = 7 +3 + 5 = 8 +3 + 6 = 9 +3 + 7 = 10 +3 + 8 = 11 +3 + 9 = 12 +3 + 10 = 13 +3 + 11 = 14 +3 + 12 = 15 +3 + 13 = 16 +3 + 14 = 17 +3 + 15 = 18 +3 + 16 = 19 +3 + 17 = 20 +3 + 18 = 21 +3 + 19 = 22 +3 + 20 = 23 +3 + 21 = 24 +3 + 22 = 25 +3 + 23 = 26 +3 + 24 = 27 +3 + 25 = 28 +3 + 26 = 29 +3 + 27 = 30 +3 + 28 = 31 +3 + 29 = 32 +3 + 30 = 33 +3 + 31 = 34 +3 + 32 = 35 +3 + 33 = 36 +3 + 34 = 37 +3 + 35 = 38 +3 + 36 = 39 +3 + 37 = 40 +3 + 38 = 41 +3 + 39 = 42 +3 + 40 = 43 +3 + 41 = 44 +3 + 42 = 45 +3 + 43 = 46 +3 + 44 = 47 +3 + 45 = 48 +3 + 46 = 49 +3 + 47 = 50 +3 + 48 = 51 +3 + 49 = 52 +3 + 50 = 53 +3 + 51 = 54 +3 + 52 = 55 +3 + 53 = 56 +3 + 54 = 57 +3 + 55 = 58 +3 + 56 = 59 +3 + 57 = 60 +3 + 58 = 61 +3 + 59 = 62 +3 + 60 = 63 +3 + 61 = 64 +3 + 62 = 65 +3 + 63 = 66 +4 + 0 = 4 +4 + 1 = 5 +4 + 2 = 6 +4 + 3 = 7 +4 + 4 = 8 +4 + 5 = 9 +4 + 6 = 10 +4 + 7 = 11 +4 + 8 = 12 +4 + 9 = 13 +4 + 10 = 14 +4 + 11 = 15 +4 + 12 = 16 +4 + 13 = 17 +4 + 14 = 18 +4 + 15 = 19 +4 + 16 = 20 +4 + 17 = 21 +4 + 18 = 22 +4 + 19 = 23 +4 + 20 = 24 +4 + 21 = 25 +4 + 22 = 26 +4 + 23 = 27 +4 + 24 = 28 +4 + 25 = 29 +4 + 26 = 30 +4 + 27 = 31 +4 + 28 = 32 +4 + 29 = 33 +4 + 30 = 34 +4 + 31 = 35 +4 + 32 = 36 +4 + 33 = 37 +4 + 34 = 38 +4 + 35 = 39 +4 + 36 = 40 +4 + 37 = 41 +4 + 38 = 42 +4 + 39 = 43 +4 + 40 = 44 +4 + 41 = 45 +4 + 42 = 46 +4 + 43 = 47 +4 + 44 = 48 +4 + 45 = 49 +4 + 46 = 50 +4 + 47 = 51 +4 + 48 = 52 +4 + 49 = 53 +4 + 50 = 54 +4 + 51 = 55 +4 + 52 = 56 +4 + 53 = 57 +4 + 54 = 58 +4 + 55 = 59 +4 + 56 = 60 +4 + 57 = 61 +4 + 58 = 62 +4 + 59 = 63 +4 + 60 = 64 +4 + 61 = 65 +4 + 62 = 66 +4 + 63 = 67 +5 + 0 = 5 +5 + 1 = 6 +5 + 2 = 7 +5 + 3 = 8 +5 + 4 = 9 +5 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+62 + 39 = 101 +62 + 40 = 102 +62 + 41 = 103 +62 + 42 = 104 +62 + 43 = 105 +62 + 44 = 106 +62 + 45 = 107 +62 + 46 = 108 +62 + 47 = 109 +62 + 48 = 110 +62 + 49 = 111 +62 + 50 = 112 +62 + 51 = 113 +62 + 52 = 114 +62 + 53 = 115 +62 + 54 = 116 +62 + 55 = 117 +62 + 56 = 118 +62 + 57 = 119 +62 + 58 = 120 +62 + 59 = 121 +62 + 60 = 122 +62 + 61 = 123 +62 + 62 = 124 +62 + 63 = 125 +63 + 0 = 63 +63 + 1 = 64 +63 + 2 = 65 +63 + 3 = 66 +63 + 4 = 67 +63 + 5 = 68 +63 + 6 = 69 +63 + 7 = 70 +63 + 8 = 71 +63 + 9 = 72 +63 + 10 = 73 +63 + 11 = 74 +63 + 12 = 75 +63 + 13 = 76 +63 + 14 = 77 +63 + 15 = 78 +63 + 16 = 79 +63 + 17 = 80 +63 + 18 = 81 +63 + 19 = 82 +63 + 20 = 83 +63 + 21 = 84 +63 + 22 = 85 +63 + 23 = 86 +63 + 24 = 87 +63 + 25 = 88 +63 + 26 = 89 +63 + 27 = 90 +63 + 28 = 91 +63 + 29 = 92 +63 + 30 = 93 +63 + 31 = 94 +63 + 32 = 95 +63 + 33 = 96 +63 + 34 = 97 +63 + 35 = 98 +63 + 36 = 99 +63 + 37 = 100 +63 + 38 = 101 +63 + 39 = 102 +63 + 40 = 103 +63 + 41 = 104 +63 + 42 = 105 +63 + 43 = 106 +63 + 44 = 107 +63 + 45 = 108 +63 + 46 = 109 +63 + 47 = 110 +63 + 48 = 111 +63 + 49 = 112 +63 + 50 = 113 +63 + 51 = 114 +63 + 52 = 115 +63 + 53 = 116 +63 + 54 = 117 +63 + 55 = 118 +63 + 56 = 119 +63 + 57 = 120 +63 + 58 = 121 +63 + 59 = 122 +63 + 60 = 123 +63 + 61 = 124 +63 + 62 = 125 +63 + 63 = 126 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_c/stimgen.h b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/stimgen.h new file mode 100644 index 000000000..7e889295c --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_c/stimgen.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimgen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /************************************/ + /* Interface Filename: stimgen.h */ + /************************************/ + +#include "systemc.h" + +SC_MODULE( stimgen ) +{ + SC_HAS_PROCESS( stimgen ); + + sc_in_clk clk; + + // Inputs + const sc_signal& result; + // Outputs + sc_signal& in1; + sc_signal& in2; + sc_signal& ready; + + // Constructor + stimgen (sc_module_name NAME, + sc_clock& TICK, + const sc_signal& RESULT, + sc_signal& IN1, + sc_signal& IN2, + sc_signal& READY ) + + : + result (RESULT), + in1 (IN1), + in2 (IN2), + ready (READY) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.cpp b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.cpp new file mode 100644 index 000000000..c3920273d --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datawidth.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /*******************************************/ + /* Implementation Filename: datawidth.cc */ + /*******************************************/ + +#include "datawidth.h" + +void +datawidth::entry() +{ + int tmp_a; + int tmp_b; + int tmp_result; + + while (true) { + + // HANDSHAKING + do { wait(); } while (ready == 0); + + // COMPUTATION + tmp_a = in1.read(); + tmp_b = in2.read(); + tmp_result = tmp_a + tmp_b; + + // WRITE OUTPUT + result.write(tmp_result); // result = in1 + in2 + wait(); + } +} diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.h b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.h new file mode 100644 index 000000000..5be0bfed9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datawidth.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /**************************************/ + /* Interface Filename: datawidth.h */ + /**************************************/ + +#include "systemc.h" + +SC_MODULE( datawidth ) +{ + SC_HAS_PROCESS( datawidth ); + + sc_in_clk clk; + + // Inputs + const sc_signal& in1; + const sc_signal& in2; + const sc_signal& ready; + // Outputs + sc_signal& result; + + // Constructor + datawidth (sc_module_name NAME, + sc_clock& TICK, + const sc_signal& IN1, + const sc_signal& IN2, + const sc_signal& READY, + sc_signal& RESULT ) + + : + in1 (IN1), + in2 (IN2), + ready (READY), + result (RESULT) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth_int.f b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth_int.f new file mode 100644 index 000000000..261078d77 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/datawidth_int.f @@ -0,0 +1,3 @@ +datawidth_int_file/datawidth.cpp +datawidth_int_file/stimgen.cpp +datawidth_int_file/main.cpp diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/golden/datawidth_int.log b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/golden/datawidth_int.log new file mode 100644 index 000000000..b168b0482 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/golden/datawidth_int.log @@ -0,0 +1,4099 @@ +SystemC Simulation +0 + 0 = 0 +0 + 1 = 1 +0 + 2 = 2 +0 + 3 = 3 +0 + 4 = 4 +0 + 5 = 5 +0 + 6 = 6 +0 + 7 = 7 +0 + 8 = 8 +0 + 9 = 9 +0 + 10 = 10 +0 + 11 = 11 +0 + 12 = 12 +0 + 13 = 13 +0 + 14 = 14 +0 + 15 = 15 +0 + 16 = 16 +0 + 17 = 17 +0 + 18 = 18 +0 + 19 = 19 +0 + 20 = 20 +0 + 21 = 21 +0 + 22 = 22 +0 + 23 = 23 +0 + 24 = 24 +0 + 25 = 25 +0 + 26 = 26 +0 + 27 = 27 +0 + 28 = 28 +0 + 29 = 29 +0 + 30 = 30 +0 + 31 = 31 +0 + 32 = 32 +0 + 33 = 33 +0 + 34 = 34 +0 + 35 = 35 +0 + 36 = 36 +0 + 37 = 37 +0 + 38 = 38 +0 + 39 = 39 +0 + 40 = 40 +0 + 41 = 41 +0 + 42 = 42 +0 + 43 = 43 +0 + 44 = 44 +0 + 45 = 45 +0 + 46 = 46 +0 + 47 = 47 +0 + 48 = 48 +0 + 49 = 49 +0 + 50 = 50 +0 + 51 = 51 +0 + 52 = 52 +0 + 53 = 53 +0 + 54 = 54 +0 + 55 = 55 +0 + 56 = 56 +0 + 57 = 57 +0 + 58 = 58 +0 + 59 = 59 +0 + 60 = 60 +0 + 61 = 61 +0 + 62 = 62 +0 + 63 = 63 +1 + 0 = 1 +1 + 1 = 2 +1 + 2 = 3 +1 + 3 = 4 +1 + 4 = 5 +1 + 5 = 6 +1 + 6 = 7 +1 + 7 = 8 +1 + 8 = 9 +1 + 9 = 10 +1 + 10 = 11 +1 + 11 = 12 +1 + 12 = 13 +1 + 13 = 14 +1 + 14 = 15 +1 + 15 = 16 +1 + 16 = 17 +1 + 17 = 18 +1 + 18 = 19 +1 + 19 = 20 +1 + 20 = 21 +1 + 21 = 22 +1 + 22 = 23 +1 + 23 = 24 +1 + 24 = 25 +1 + 25 = 26 +1 + 26 = 27 +1 + 27 = 28 +1 + 28 = 29 +1 + 29 = 30 +1 + 30 = 31 +1 + 31 = 32 +1 + 32 = 33 +1 + 33 = 34 +1 + 34 = 35 +1 + 35 = 36 +1 + 36 = 37 +1 + 37 = 38 +1 + 38 = 39 +1 + 39 = 40 +1 + 40 = 41 +1 + 41 = 42 +1 + 42 = 43 +1 + 43 = 44 +1 + 44 = 45 +1 + 45 = 46 +1 + 46 = 47 +1 + 47 = 48 +1 + 48 = 49 +1 + 49 = 50 +1 + 50 = 51 +1 + 51 = 52 +1 + 52 = 53 +1 + 53 = 54 +1 + 54 = 55 +1 + 55 = 56 +1 + 56 = 57 +1 + 57 = 58 +1 + 58 = 59 +1 + 59 = 60 +1 + 60 = 61 +1 + 61 = 62 +1 + 62 = 63 +1 + 63 = 64 +2 + 0 = 2 +2 + 1 = 3 +2 + 2 = 4 +2 + 3 = 5 +2 + 4 = 6 +2 + 5 = 7 +2 + 6 = 8 +2 + 7 = 9 +2 + 8 = 10 +2 + 9 = 11 +2 + 10 = 12 +2 + 11 = 13 +2 + 12 = 14 +2 + 13 = 15 +2 + 14 = 16 +2 + 15 = 17 +2 + 16 = 18 +2 + 17 = 19 +2 + 18 = 20 +2 + 19 = 21 +2 + 20 = 22 +2 + 21 = 23 +2 + 22 = 24 +2 + 23 = 25 +2 + 24 = 26 +2 + 25 = 27 +2 + 26 = 28 +2 + 27 = 29 +2 + 28 = 30 +2 + 29 = 31 +2 + 30 = 32 +2 + 31 = 33 +2 + 32 = 34 +2 + 33 = 35 +2 + 34 = 36 +2 + 35 = 37 +2 + 36 = 38 +2 + 37 = 39 +2 + 38 = 40 +2 + 39 = 41 +2 + 40 = 42 +2 + 41 = 43 +2 + 42 = 44 +2 + 43 = 45 +2 + 44 = 46 +2 + 45 = 47 +2 + 46 = 48 +2 + 47 = 49 +2 + 48 = 50 +2 + 49 = 51 +2 + 50 = 52 +2 + 51 = 53 +2 + 52 = 54 +2 + 53 = 55 +2 + 54 = 56 +2 + 55 = 57 +2 + 56 = 58 +2 + 57 = 59 +2 + 58 = 60 +2 + 59 = 61 +2 + 60 = 62 +2 + 61 = 63 +2 + 62 = 64 +2 + 63 = 65 +3 + 0 = 3 +3 + 1 = 4 +3 + 2 = 5 +3 + 3 = 6 +3 + 4 = 7 +3 + 5 = 8 +3 + 6 = 9 +3 + 7 = 10 +3 + 8 = 11 +3 + 9 = 12 +3 + 10 = 13 +3 + 11 = 14 +3 + 12 = 15 +3 + 13 = 16 +3 + 14 = 17 +3 + 15 = 18 +3 + 16 = 19 +3 + 17 = 20 +3 + 18 = 21 +3 + 19 = 22 +3 + 20 = 23 +3 + 21 = 24 +3 + 22 = 25 +3 + 23 = 26 +3 + 24 = 27 +3 + 25 = 28 +3 + 26 = 29 +3 + 27 = 30 +3 + 28 = 31 +3 + 29 = 32 +3 + 30 = 33 +3 + 31 = 34 +3 + 32 = 35 +3 + 33 = 36 +3 + 34 = 37 +3 + 35 = 38 +3 + 36 = 39 +3 + 37 = 40 +3 + 38 = 41 +3 + 39 = 42 +3 + 40 = 43 +3 + 41 = 44 +3 + 42 = 45 +3 + 43 = 46 +3 + 44 = 47 +3 + 45 = 48 +3 + 46 = 49 +3 + 47 = 50 +3 + 48 = 51 +3 + 49 = 52 +3 + 50 = 53 +3 + 51 = 54 +3 + 52 = 55 +3 + 53 = 56 +3 + 54 = 57 +3 + 55 = 58 +3 + 56 = 59 +3 + 57 = 60 +3 + 58 = 61 +3 + 59 = 62 +3 + 60 = 63 +3 + 61 = 64 +3 + 62 = 65 +3 + 63 = 66 +4 + 0 = 4 +4 + 1 = 5 +4 + 2 = 6 +4 + 3 = 7 +4 + 4 = 8 +4 + 5 = 9 +4 + 6 = 10 +4 + 7 = 11 +4 + 8 = 12 +4 + 9 = 13 +4 + 10 = 14 +4 + 11 = 15 +4 + 12 = 16 +4 + 13 = 17 +4 + 14 = 18 +4 + 15 = 19 +4 + 16 = 20 +4 + 17 = 21 +4 + 18 = 22 +4 + 19 = 23 +4 + 20 = 24 +4 + 21 = 25 +4 + 22 = 26 +4 + 23 = 27 +4 + 24 = 28 +4 + 25 = 29 +4 + 26 = 30 +4 + 27 = 31 +4 + 28 = 32 +4 + 29 = 33 +4 + 30 = 34 +4 + 31 = 35 +4 + 32 = 36 +4 + 33 = 37 +4 + 34 = 38 +4 + 35 = 39 +4 + 36 = 40 +4 + 37 = 41 +4 + 38 = 42 +4 + 39 = 43 +4 + 40 = 44 +4 + 41 = 45 +4 + 42 = 46 +4 + 43 = 47 +4 + 44 = 48 +4 + 45 = 49 +4 + 46 = 50 +4 + 47 = 51 +4 + 48 = 52 +4 + 49 = 53 +4 + 50 = 54 +4 + 51 = 55 +4 + 52 = 56 +4 + 53 = 57 +4 + 54 = 58 +4 + 55 = 59 +4 + 56 = 60 +4 + 57 = 61 +4 + 58 = 62 +4 + 59 = 63 +4 + 60 = 64 +4 + 61 = 65 +4 + 62 = 66 +4 + 63 = 67 +5 + 0 = 5 +5 + 1 = 6 +5 + 2 = 7 +5 + 3 = 8 +5 + 4 = 9 +5 + 5 = 10 +5 + 6 = 11 +5 + 7 = 12 +5 + 8 = 13 +5 + 9 = 14 +5 + 10 = 15 +5 + 11 = 16 +5 + 12 = 17 +5 + 13 = 18 +5 + 14 = 19 +5 + 15 = 20 +5 + 16 = 21 +5 + 17 = 22 +5 + 18 = 23 +5 + 19 = 24 +5 + 20 = 25 +5 + 21 = 26 +5 + 22 = 27 +5 + 23 = 28 +5 + 24 = 29 +5 + 25 = 30 +5 + 26 = 31 +5 + 27 = 32 +5 + 28 = 33 +5 + 29 = 34 +5 + 30 = 35 +5 + 31 = 36 +5 + 32 = 37 +5 + 33 = 38 +5 + 34 = 39 +5 + 35 = 40 +5 + 36 = 41 +5 + 37 = 42 +5 + 38 = 43 +5 + 39 = 44 +5 + 40 = 45 +5 + 41 = 46 +5 + 42 = 47 +5 + 43 = 48 +5 + 44 = 49 +5 + 45 = 50 +5 + 46 = 51 +5 + 47 = 52 +5 + 48 = 53 +5 + 49 = 54 +5 + 50 = 55 +5 + 51 = 56 +5 + 52 = 57 +5 + 53 = 58 +5 + 54 = 59 +5 + 55 = 60 +5 + 56 = 61 +5 + 57 = 62 +5 + 58 = 63 +5 + 59 = 64 +5 + 60 = 65 +5 + 61 = 66 +5 + 62 = 67 +5 + 63 = 68 +6 + 0 = 6 +6 + 1 = 7 +6 + 2 = 8 +6 + 3 = 9 +6 + 4 = 10 +6 + 5 = 11 +6 + 6 = 12 +6 + 7 = 13 +6 + 8 = 14 +6 + 9 = 15 +6 + 10 = 16 +6 + 11 = 17 +6 + 12 = 18 +6 + 13 = 19 +6 + 14 = 20 +6 + 15 = 21 +6 + 16 = 22 +6 + 17 = 23 +6 + 18 = 24 +6 + 19 = 25 +6 + 20 = 26 +6 + 21 = 27 +6 + 22 = 28 +6 + 23 = 29 +6 + 24 = 30 +6 + 25 = 31 +6 + 26 = 32 +6 + 27 = 33 +6 + 28 = 34 +6 + 29 = 35 +6 + 30 = 36 +6 + 31 = 37 +6 + 32 = 38 +6 + 33 = 39 +6 + 34 = 40 +6 + 35 = 41 +6 + 36 = 42 +6 + 37 = 43 +6 + 38 = 44 +6 + 39 = 45 +6 + 40 = 46 +6 + 41 = 47 +6 + 42 = 48 +6 + 43 = 49 +6 + 44 = 50 +6 + 45 = 51 +6 + 46 = 52 +6 + 47 = 53 +6 + 48 = 54 +6 + 49 = 55 +6 + 50 = 56 +6 + 51 = 57 +6 + 52 = 58 +6 + 53 = 59 +6 + 54 = 60 +6 + 55 = 61 +6 + 56 = 62 +6 + 57 = 63 +6 + 58 = 64 +6 + 59 = 65 +6 + 60 = 66 +6 + 61 = 67 +6 + 62 = 68 +6 + 63 = 69 +7 + 0 = 7 +7 + 1 = 8 +7 + 2 = 9 +7 + 3 = 10 +7 + 4 = 11 +7 + 5 = 12 +7 + 6 = 13 +7 + 7 = 14 +7 + 8 = 15 +7 + 9 = 16 +7 + 10 = 17 +7 + 11 = 18 +7 + 12 = 19 +7 + 13 = 20 +7 + 14 = 21 +7 + 15 = 22 +7 + 16 = 23 +7 + 17 = 24 +7 + 18 = 25 +7 + 19 = 26 +7 + 20 = 27 +7 + 21 = 28 +7 + 22 = 29 +7 + 23 = 30 +7 + 24 = 31 +7 + 25 = 32 +7 + 26 = 33 +7 + 27 = 34 +7 + 28 = 35 +7 + 29 = 36 +7 + 30 = 37 +7 + 31 = 38 +7 + 32 = 39 +7 + 33 = 40 +7 + 34 = 41 +7 + 35 = 42 +7 + 36 = 43 +7 + 37 = 44 +7 + 38 = 45 +7 + 39 = 46 +7 + 40 = 47 +7 + 41 = 48 +7 + 42 = 49 +7 + 43 = 50 +7 + 44 = 51 +7 + 45 = 52 +7 + 46 = 53 +7 + 47 = 54 +7 + 48 = 55 +7 + 49 = 56 +7 + 50 = 57 +7 + 51 = 58 +7 + 52 = 59 +7 + 53 = 60 +7 + 54 = 61 +7 + 55 = 62 +7 + 56 = 63 +7 + 57 = 64 +7 + 58 = 65 +7 + 59 = 66 +7 + 60 = 67 +7 + 61 = 68 +7 + 62 = 69 +7 + 63 = 70 +8 + 0 = 8 +8 + 1 = 9 +8 + 2 = 10 +8 + 3 = 11 +8 + 4 = 12 +8 + 5 = 13 +8 + 6 = 14 +8 + 7 = 15 +8 + 8 = 16 +8 + 9 = 17 +8 + 10 = 18 +8 + 11 = 19 +8 + 12 = 20 +8 + 13 = 21 +8 + 14 = 22 +8 + 15 = 23 +8 + 16 = 24 +8 + 17 = 25 +8 + 18 = 26 +8 + 19 = 27 +8 + 20 = 28 +8 + 21 = 29 +8 + 22 = 30 +8 + 23 = 31 +8 + 24 = 32 +8 + 25 = 33 +8 + 26 = 34 +8 + 27 = 35 +8 + 28 = 36 +8 + 29 = 37 +8 + 30 = 38 +8 + 31 = 39 +8 + 32 = 40 +8 + 33 = 41 +8 + 34 = 42 +8 + 35 = 43 +8 + 36 = 44 +8 + 37 = 45 +8 + 38 = 46 +8 + 39 = 47 +8 + 40 = 48 +8 + 41 = 49 +8 + 42 = 50 +8 + 43 = 51 +8 + 44 = 52 +8 + 45 = 53 +8 + 46 = 54 +8 + 47 = 55 +8 + 48 = 56 +8 + 49 = 57 +8 + 50 = 58 +8 + 51 = 59 +8 + 52 = 60 +8 + 53 = 61 +8 + 54 = 62 +8 + 55 = 63 +8 + 56 = 64 +8 + 57 = 65 +8 + 58 = 66 +8 + 59 = 67 +8 + 60 = 68 +8 + 61 = 69 +8 + 62 = 70 +8 + 63 = 71 +9 + 0 = 9 +9 + 1 = 10 +9 + 2 = 11 +9 + 3 = 12 +9 + 4 = 13 +9 + 5 = 14 +9 + 6 = 15 +9 + 7 = 16 +9 + 8 = 17 +9 + 9 = 18 +9 + 10 = 19 +9 + 11 = 20 +9 + 12 = 21 +9 + 13 = 22 +9 + 14 = 23 +9 + 15 = 24 +9 + 16 = 25 +9 + 17 = 26 +9 + 18 = 27 +9 + 19 = 28 +9 + 20 = 29 +9 + 21 = 30 +9 + 22 = 31 +9 + 23 = 32 +9 + 24 = 33 +9 + 25 = 34 +9 + 26 = 35 +9 + 27 = 36 +9 + 28 = 37 +9 + 29 = 38 +9 + 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+ 50 = 97 +47 + 51 = 98 +47 + 52 = 99 +47 + 53 = 100 +47 + 54 = 101 +47 + 55 = 102 +47 + 56 = 103 +47 + 57 = 104 +47 + 58 = 105 +47 + 59 = 106 +47 + 60 = 107 +47 + 61 = 108 +47 + 62 = 109 +47 + 63 = 110 +48 + 0 = 48 +48 + 1 = 49 +48 + 2 = 50 +48 + 3 = 51 +48 + 4 = 52 +48 + 5 = 53 +48 + 6 = 54 +48 + 7 = 55 +48 + 8 = 56 +48 + 9 = 57 +48 + 10 = 58 +48 + 11 = 59 +48 + 12 = 60 +48 + 13 = 61 +48 + 14 = 62 +48 + 15 = 63 +48 + 16 = 64 +48 + 17 = 65 +48 + 18 = 66 +48 + 19 = 67 +48 + 20 = 68 +48 + 21 = 69 +48 + 22 = 70 +48 + 23 = 71 +48 + 24 = 72 +48 + 25 = 73 +48 + 26 = 74 +48 + 27 = 75 +48 + 28 = 76 +48 + 29 = 77 +48 + 30 = 78 +48 + 31 = 79 +48 + 32 = 80 +48 + 33 = 81 +48 + 34 = 82 +48 + 35 = 83 +48 + 36 = 84 +48 + 37 = 85 +48 + 38 = 86 +48 + 39 = 87 +48 + 40 = 88 +48 + 41 = 89 +48 + 42 = 90 +48 + 43 = 91 +48 + 44 = 92 +48 + 45 = 93 +48 + 46 = 94 +48 + 47 = 95 +48 + 48 = 96 +48 + 49 = 97 +48 + 50 = 98 +48 + 51 = 99 +48 + 52 = 100 +48 + 53 = 101 +48 + 54 = 102 +48 + 55 = 103 +48 + 56 = 104 +48 + 57 = 105 +48 + 58 = 106 +48 + 59 = 107 +48 + 60 = 108 +48 + 61 = 109 +48 + 62 = 110 +48 + 63 = 111 +49 + 0 = 49 +49 + 1 = 50 +49 + 2 = 51 +49 + 3 = 52 +49 + 4 = 53 +49 + 5 = 54 +49 + 6 = 55 +49 + 7 = 56 +49 + 8 = 57 +49 + 9 = 58 +49 + 10 = 59 +49 + 11 = 60 +49 + 12 = 61 +49 + 13 = 62 +49 + 14 = 63 +49 + 15 = 64 +49 + 16 = 65 +49 + 17 = 66 +49 + 18 = 67 +49 + 19 = 68 +49 + 20 = 69 +49 + 21 = 70 +49 + 22 = 71 +49 + 23 = 72 +49 + 24 = 73 +49 + 25 = 74 +49 + 26 = 75 +49 + 27 = 76 +49 + 28 = 77 +49 + 29 = 78 +49 + 30 = 79 +49 + 31 = 80 +49 + 32 = 81 +49 + 33 = 82 +49 + 34 = 83 +49 + 35 = 84 +49 + 36 = 85 +49 + 37 = 86 +49 + 38 = 87 +49 + 39 = 88 +49 + 40 = 89 +49 + 41 = 90 +49 + 42 = 91 +49 + 43 = 92 +49 + 44 = 93 +49 + 45 = 94 +49 + 46 = 95 +49 + 47 = 96 +49 + 48 = 97 +49 + 49 = 98 +49 + 50 = 99 +49 + 51 = 100 +49 + 52 = 101 +49 + 53 = 102 +49 + 54 = 103 +49 + 55 = 104 +49 + 56 = 105 +49 + 57 = 106 +49 + 58 = 107 +49 + 59 = 108 +49 + 60 = 109 +49 + 61 = 110 +49 + 62 = 111 +49 + 63 = 112 +50 + 0 = 50 +50 + 1 = 51 +50 + 2 = 52 +50 + 3 = 53 +50 + 4 = 54 +50 + 5 = 55 +50 + 6 = 56 +50 + 7 = 57 +50 + 8 = 58 +50 + 9 = 59 +50 + 10 = 60 +50 + 11 = 61 +50 + 12 = 62 +50 + 13 = 63 +50 + 14 = 64 +50 + 15 = 65 +50 + 16 = 66 +50 + 17 = 67 +50 + 18 = 68 +50 + 19 = 69 +50 + 20 = 70 +50 + 21 = 71 +50 + 22 = 72 +50 + 23 = 73 +50 + 24 = 74 +50 + 25 = 75 +50 + 26 = 76 +50 + 27 = 77 +50 + 28 = 78 +50 + 29 = 79 +50 + 30 = 80 +50 + 31 = 81 +50 + 32 = 82 +50 + 33 = 83 +50 + 34 = 84 +50 + 35 = 85 +50 + 36 = 86 +50 + 37 = 87 +50 + 38 = 88 +50 + 39 = 89 +50 + 40 = 90 +50 + 41 = 91 +50 + 42 = 92 +50 + 43 = 93 +50 + 44 = 94 +50 + 45 = 95 +50 + 46 = 96 +50 + 47 = 97 +50 + 48 = 98 +50 + 49 = 99 +50 + 50 = 100 +50 + 51 = 101 +50 + 52 = 102 +50 + 53 = 103 +50 + 54 = 104 +50 + 55 = 105 +50 + 56 = 106 +50 + 57 = 107 +50 + 58 = 108 +50 + 59 = 109 +50 + 60 = 110 +50 + 61 = 111 +50 + 62 = 112 +50 + 63 = 113 +51 + 0 = 51 +51 + 1 = 52 +51 + 2 = 53 +51 + 3 = 54 +51 + 4 = 55 +51 + 5 = 56 +51 + 6 = 57 +51 + 7 = 58 +51 + 8 = 59 +51 + 9 = 60 +51 + 10 = 61 +51 + 11 = 62 +51 + 12 = 63 +51 + 13 = 64 +51 + 14 = 65 +51 + 15 = 66 +51 + 16 = 67 +51 + 17 = 68 +51 + 18 = 69 +51 + 19 = 70 +51 + 20 = 71 +51 + 21 = 72 +51 + 22 = 73 +51 + 23 = 74 +51 + 24 = 75 +51 + 25 = 76 +51 + 26 = 77 +51 + 27 = 78 +51 + 28 = 79 +51 + 29 = 80 +51 + 30 = 81 +51 + 31 = 82 +51 + 32 = 83 +51 + 33 = 84 +51 + 34 = 85 +51 + 35 = 86 +51 + 36 = 87 +51 + 37 = 88 +51 + 38 = 89 +51 + 39 = 90 +51 + 40 = 91 +51 + 41 = 92 +51 + 42 = 93 +51 + 43 = 94 +51 + 44 = 95 +51 + 45 = 96 +51 + 46 = 97 +51 + 47 = 98 +51 + 48 = 99 +51 + 49 = 100 +51 + 50 = 101 +51 + 51 = 102 +51 + 52 = 103 +51 + 53 = 104 +51 + 54 = 105 +51 + 55 = 106 +51 + 56 = 107 +51 + 57 = 108 +51 + 58 = 109 +51 + 59 = 110 +51 + 60 = 111 +51 + 61 = 112 +51 + 62 = 113 +51 + 63 = 114 +52 + 0 = 52 +52 + 1 = 53 +52 + 2 = 54 +52 + 3 = 55 +52 + 4 = 56 +52 + 5 = 57 +52 + 6 = 58 +52 + 7 = 59 +52 + 8 = 60 +52 + 9 = 61 +52 + 10 = 62 +52 + 11 = 63 +52 + 12 = 64 +52 + 13 = 65 +52 + 14 = 66 +52 + 15 = 67 +52 + 16 = 68 +52 + 17 = 69 +52 + 18 = 70 +52 + 19 = 71 +52 + 20 = 72 +52 + 21 = 73 +52 + 22 = 74 +52 + 23 = 75 +52 + 24 = 76 +52 + 25 = 77 +52 + 26 = 78 +52 + 27 = 79 +52 + 28 = 80 +52 + 29 = 81 +52 + 30 = 82 +52 + 31 = 83 +52 + 32 = 84 +52 + 33 = 85 +52 + 34 = 86 +52 + 35 = 87 +52 + 36 = 88 +52 + 37 = 89 +52 + 38 = 90 +52 + 39 = 91 +52 + 40 = 92 +52 + 41 = 93 +52 + 42 = 94 +52 + 43 = 95 +52 + 44 = 96 +52 + 45 = 97 +52 + 46 = 98 +52 + 47 = 99 +52 + 48 = 100 +52 + 49 = 101 +52 + 50 = 102 +52 + 51 = 103 +52 + 52 = 104 +52 + 53 = 105 +52 + 54 = 106 +52 + 55 = 107 +52 + 56 = 108 +52 + 57 = 109 +52 + 58 = 110 +52 + 59 = 111 +52 + 60 = 112 +52 + 61 = 113 +52 + 62 = 114 +52 + 63 = 115 +53 + 0 = 53 +53 + 1 = 54 +53 + 2 = 55 +53 + 3 = 56 +53 + 4 = 57 +53 + 5 = 58 +53 + 6 = 59 +53 + 7 = 60 +53 + 8 = 61 +53 + 9 = 62 +53 + 10 = 63 +53 + 11 = 64 +53 + 12 = 65 +53 + 13 = 66 +53 + 14 = 67 +53 + 15 = 68 +53 + 16 = 69 +53 + 17 = 70 +53 + 18 = 71 +53 + 19 = 72 +53 + 20 = 73 +53 + 21 = 74 +53 + 22 = 75 +53 + 23 = 76 +53 + 24 = 77 +53 + 25 = 78 +53 + 26 = 79 +53 + 27 = 80 +53 + 28 = 81 +53 + 29 = 82 +53 + 30 = 83 +53 + 31 = 84 +53 + 32 = 85 +53 + 33 = 86 +53 + 34 = 87 +53 + 35 = 88 +53 + 36 = 89 +53 + 37 = 90 +53 + 38 = 91 +53 + 39 = 92 +53 + 40 = 93 +53 + 41 = 94 +53 + 42 = 95 +53 + 43 = 96 +53 + 44 = 97 +53 + 45 = 98 +53 + 46 = 99 +53 + 47 = 100 +53 + 48 = 101 +53 + 49 = 102 +53 + 50 = 103 +53 + 51 = 104 +53 + 52 = 105 +53 + 53 = 106 +53 + 54 = 107 +53 + 55 = 108 +53 + 56 = 109 +53 + 57 = 110 +53 + 58 = 111 +53 + 59 = 112 +53 + 60 = 113 +53 + 61 = 114 +53 + 62 = 115 +53 + 63 = 116 +54 + 0 = 54 +54 + 1 = 55 +54 + 2 = 56 +54 + 3 = 57 +54 + 4 = 58 +54 + 5 = 59 +54 + 6 = 60 +54 + 7 = 61 +54 + 8 = 62 +54 + 9 = 63 +54 + 10 = 64 +54 + 11 = 65 +54 + 12 = 66 +54 + 13 = 67 +54 + 14 = 68 +54 + 15 = 69 +54 + 16 = 70 +54 + 17 = 71 +54 + 18 = 72 +54 + 19 = 73 +54 + 20 = 74 +54 + 21 = 75 +54 + 22 = 76 +54 + 23 = 77 +54 + 24 = 78 +54 + 25 = 79 +54 + 26 = 80 +54 + 27 = 81 +54 + 28 = 82 +54 + 29 = 83 +54 + 30 = 84 +54 + 31 = 85 +54 + 32 = 86 +54 + 33 = 87 +54 + 34 = 88 +54 + 35 = 89 +54 + 36 = 90 +54 + 37 = 91 +54 + 38 = 92 +54 + 39 = 93 +54 + 40 = 94 +54 + 41 = 95 +54 + 42 = 96 +54 + 43 = 97 +54 + 44 = 98 +54 + 45 = 99 +54 + 46 = 100 +54 + 47 = 101 +54 + 48 = 102 +54 + 49 = 103 +54 + 50 = 104 +54 + 51 = 105 +54 + 52 = 106 +54 + 53 = 107 +54 + 54 = 108 +54 + 55 = 109 +54 + 56 = 110 +54 + 57 = 111 +54 + 58 = 112 +54 + 59 = 113 +54 + 60 = 114 +54 + 61 = 115 +54 + 62 = 116 +54 + 63 = 117 +55 + 0 = 55 +55 + 1 = 56 +55 + 2 = 57 +55 + 3 = 58 +55 + 4 = 59 +55 + 5 = 60 +55 + 6 = 61 +55 + 7 = 62 +55 + 8 = 63 +55 + 9 = 64 +55 + 10 = 65 +55 + 11 = 66 +55 + 12 = 67 +55 + 13 = 68 +55 + 14 = 69 +55 + 15 = 70 +55 + 16 = 71 +55 + 17 = 72 +55 + 18 = 73 +55 + 19 = 74 +55 + 20 = 75 +55 + 21 = 76 +55 + 22 = 77 +55 + 23 = 78 +55 + 24 = 79 +55 + 25 = 80 +55 + 26 = 81 +55 + 27 = 82 +55 + 28 = 83 +55 + 29 = 84 +55 + 30 = 85 +55 + 31 = 86 +55 + 32 = 87 +55 + 33 = 88 +55 + 34 = 89 +55 + 35 = 90 +55 + 36 = 91 +55 + 37 = 92 +55 + 38 = 93 +55 + 39 = 94 +55 + 40 = 95 +55 + 41 = 96 +55 + 42 = 97 +55 + 43 = 98 +55 + 44 = 99 +55 + 45 = 100 +55 + 46 = 101 +55 + 47 = 102 +55 + 48 = 103 +55 + 49 = 104 +55 + 50 = 105 +55 + 51 = 106 +55 + 52 = 107 +55 + 53 = 108 +55 + 54 = 109 +55 + 55 = 110 +55 + 56 = 111 +55 + 57 = 112 +55 + 58 = 113 +55 + 59 = 114 +55 + 60 = 115 +55 + 61 = 116 +55 + 62 = 117 +55 + 63 = 118 +56 + 0 = 56 +56 + 1 = 57 +56 + 2 = 58 +56 + 3 = 59 +56 + 4 = 60 +56 + 5 = 61 +56 + 6 = 62 +56 + 7 = 63 +56 + 8 = 64 +56 + 9 = 65 +56 + 10 = 66 +56 + 11 = 67 +56 + 12 = 68 +56 + 13 = 69 +56 + 14 = 70 +56 + 15 = 71 +56 + 16 = 72 +56 + 17 = 73 +56 + 18 = 74 +56 + 19 = 75 +56 + 20 = 76 +56 + 21 = 77 +56 + 22 = 78 +56 + 23 = 79 +56 + 24 = 80 +56 + 25 = 81 +56 + 26 = 82 +56 + 27 = 83 +56 + 28 = 84 +56 + 29 = 85 +56 + 30 = 86 +56 + 31 = 87 +56 + 32 = 88 +56 + 33 = 89 +56 + 34 = 90 +56 + 35 = 91 +56 + 36 = 92 +56 + 37 = 93 +56 + 38 = 94 +56 + 39 = 95 +56 + 40 = 96 +56 + 41 = 97 +56 + 42 = 98 +56 + 43 = 99 +56 + 44 = 100 +56 + 45 = 101 +56 + 46 = 102 +56 + 47 = 103 +56 + 48 = 104 +56 + 49 = 105 +56 + 50 = 106 +56 + 51 = 107 +56 + 52 = 108 +56 + 53 = 109 +56 + 54 = 110 +56 + 55 = 111 +56 + 56 = 112 +56 + 57 = 113 +56 + 58 = 114 +56 + 59 = 115 +56 + 60 = 116 +56 + 61 = 117 +56 + 62 = 118 +56 + 63 = 119 +57 + 0 = 57 +57 + 1 = 58 +57 + 2 = 59 +57 + 3 = 60 +57 + 4 = 61 +57 + 5 = 62 +57 + 6 = 63 +57 + 7 = 64 +57 + 8 = 65 +57 + 9 = 66 +57 + 10 = 67 +57 + 11 = 68 +57 + 12 = 69 +57 + 13 = 70 +57 + 14 = 71 +57 + 15 = 72 +57 + 16 = 73 +57 + 17 = 74 +57 + 18 = 75 +57 + 19 = 76 +57 + 20 = 77 +57 + 21 = 78 +57 + 22 = 79 +57 + 23 = 80 +57 + 24 = 81 +57 + 25 = 82 +57 + 26 = 83 +57 + 27 = 84 +57 + 28 = 85 +57 + 29 = 86 +57 + 30 = 87 +57 + 31 = 88 +57 + 32 = 89 +57 + 33 = 90 +57 + 34 = 91 +57 + 35 = 92 +57 + 36 = 93 +57 + 37 = 94 +57 + 38 = 95 +57 + 39 = 96 +57 + 40 = 97 +57 + 41 = 98 +57 + 42 = 99 +57 + 43 = 100 +57 + 44 = 101 +57 + 45 = 102 +57 + 46 = 103 +57 + 47 = 104 +57 + 48 = 105 +57 + 49 = 106 +57 + 50 = 107 +57 + 51 = 108 +57 + 52 = 109 +57 + 53 = 110 +57 + 54 = 111 +57 + 55 = 112 +57 + 56 = 113 +57 + 57 = 114 +57 + 58 = 115 +57 + 59 = 116 +57 + 60 = 117 +57 + 61 = 118 +57 + 62 = 119 +57 + 63 = 120 +58 + 0 = 58 +58 + 1 = 59 +58 + 2 = 60 +58 + 3 = 61 +58 + 4 = 62 +58 + 5 = 63 +58 + 6 = 64 +58 + 7 = 65 +58 + 8 = 66 +58 + 9 = 67 +58 + 10 = 68 +58 + 11 = 69 +58 + 12 = 70 +58 + 13 = 71 +58 + 14 = 72 +58 + 15 = 73 +58 + 16 = 74 +58 + 17 = 75 +58 + 18 = 76 +58 + 19 = 77 +58 + 20 = 78 +58 + 21 = 79 +58 + 22 = 80 +58 + 23 = 81 +58 + 24 = 82 +58 + 25 = 83 +58 + 26 = 84 +58 + 27 = 85 +58 + 28 = 86 +58 + 29 = 87 +58 + 30 = 88 +58 + 31 = 89 +58 + 32 = 90 +58 + 33 = 91 +58 + 34 = 92 +58 + 35 = 93 +58 + 36 = 94 +58 + 37 = 95 +58 + 38 = 96 +58 + 39 = 97 +58 + 40 = 98 +58 + 41 = 99 +58 + 42 = 100 +58 + 43 = 101 +58 + 44 = 102 +58 + 45 = 103 +58 + 46 = 104 +58 + 47 = 105 +58 + 48 = 106 +58 + 49 = 107 +58 + 50 = 108 +58 + 51 = 109 +58 + 52 = 110 +58 + 53 = 111 +58 + 54 = 112 +58 + 55 = 113 +58 + 56 = 114 +58 + 57 = 115 +58 + 58 = 116 +58 + 59 = 117 +58 + 60 = 118 +58 + 61 = 119 +58 + 62 = 120 +58 + 63 = 121 +59 + 0 = 59 +59 + 1 = 60 +59 + 2 = 61 +59 + 3 = 62 +59 + 4 = 63 +59 + 5 = 64 +59 + 6 = 65 +59 + 7 = 66 +59 + 8 = 67 +59 + 9 = 68 +59 + 10 = 69 +59 + 11 = 70 +59 + 12 = 71 +59 + 13 = 72 +59 + 14 = 73 +59 + 15 = 74 +59 + 16 = 75 +59 + 17 = 76 +59 + 18 = 77 +59 + 19 = 78 +59 + 20 = 79 +59 + 21 = 80 +59 + 22 = 81 +59 + 23 = 82 +59 + 24 = 83 +59 + 25 = 84 +59 + 26 = 85 +59 + 27 = 86 +59 + 28 = 87 +59 + 29 = 88 +59 + 30 = 89 +59 + 31 = 90 +59 + 32 = 91 +59 + 33 = 92 +59 + 34 = 93 +59 + 35 = 94 +59 + 36 = 95 +59 + 37 = 96 +59 + 38 = 97 +59 + 39 = 98 +59 + 40 = 99 +59 + 41 = 100 +59 + 42 = 101 +59 + 43 = 102 +59 + 44 = 103 +59 + 45 = 104 +59 + 46 = 105 +59 + 47 = 106 +59 + 48 = 107 +59 + 49 = 108 +59 + 50 = 109 +59 + 51 = 110 +59 + 52 = 111 +59 + 53 = 112 +59 + 54 = 113 +59 + 55 = 114 +59 + 56 = 115 +59 + 57 = 116 +59 + 58 = 117 +59 + 59 = 118 +59 + 60 = 119 +59 + 61 = 120 +59 + 62 = 121 +59 + 63 = 122 +60 + 0 = 60 +60 + 1 = 61 +60 + 2 = 62 +60 + 3 = 63 +60 + 4 = 64 +60 + 5 = 65 +60 + 6 = 66 +60 + 7 = 67 +60 + 8 = 68 +60 + 9 = 69 +60 + 10 = 70 +60 + 11 = 71 +60 + 12 = 72 +60 + 13 = 73 +60 + 14 = 74 +60 + 15 = 75 +60 + 16 = 76 +60 + 17 = 77 +60 + 18 = 78 +60 + 19 = 79 +60 + 20 = 80 +60 + 21 = 81 +60 + 22 = 82 +60 + 23 = 83 +60 + 24 = 84 +60 + 25 = 85 +60 + 26 = 86 +60 + 27 = 87 +60 + 28 = 88 +60 + 29 = 89 +60 + 30 = 90 +60 + 31 = 91 +60 + 32 = 92 +60 + 33 = 93 +60 + 34 = 94 +60 + 35 = 95 +60 + 36 = 96 +60 + 37 = 97 +60 + 38 = 98 +60 + 39 = 99 +60 + 40 = 100 +60 + 41 = 101 +60 + 42 = 102 +60 + 43 = 103 +60 + 44 = 104 +60 + 45 = 105 +60 + 46 = 106 +60 + 47 = 107 +60 + 48 = 108 +60 + 49 = 109 +60 + 50 = 110 +60 + 51 = 111 +60 + 52 = 112 +60 + 53 = 113 +60 + 54 = 114 +60 + 55 = 115 +60 + 56 = 116 +60 + 57 = 117 +60 + 58 = 118 +60 + 59 = 119 +60 + 60 = 120 +60 + 61 = 121 +60 + 62 = 122 +60 + 63 = 123 +61 + 0 = 61 +61 + 1 = 62 +61 + 2 = 63 +61 + 3 = 64 +61 + 4 = 65 +61 + 5 = 66 +61 + 6 = 67 +61 + 7 = 68 +61 + 8 = 69 +61 + 9 = 70 +61 + 10 = 71 +61 + 11 = 72 +61 + 12 = 73 +61 + 13 = 74 +61 + 14 = 75 +61 + 15 = 76 +61 + 16 = 77 +61 + 17 = 78 +61 + 18 = 79 +61 + 19 = 80 +61 + 20 = 81 +61 + 21 = 82 +61 + 22 = 83 +61 + 23 = 84 +61 + 24 = 85 +61 + 25 = 86 +61 + 26 = 87 +61 + 27 = 88 +61 + 28 = 89 +61 + 29 = 90 +61 + 30 = 91 +61 + 31 = 92 +61 + 32 = 93 +61 + 33 = 94 +61 + 34 = 95 +61 + 35 = 96 +61 + 36 = 97 +61 + 37 = 98 +61 + 38 = 99 +61 + 39 = 100 +61 + 40 = 101 +61 + 41 = 102 +61 + 42 = 103 +61 + 43 = 104 +61 + 44 = 105 +61 + 45 = 106 +61 + 46 = 107 +61 + 47 = 108 +61 + 48 = 109 +61 + 49 = 110 +61 + 50 = 111 +61 + 51 = 112 +61 + 52 = 113 +61 + 53 = 114 +61 + 54 = 115 +61 + 55 = 116 +61 + 56 = 117 +61 + 57 = 118 +61 + 58 = 119 +61 + 59 = 120 +61 + 60 = 121 +61 + 61 = 122 +61 + 62 = 123 +61 + 63 = 124 +62 + 0 = 62 +62 + 1 = 63 +62 + 2 = 64 +62 + 3 = 65 +62 + 4 = 66 +62 + 5 = 67 +62 + 6 = 68 +62 + 7 = 69 +62 + 8 = 70 +62 + 9 = 71 +62 + 10 = 72 +62 + 11 = 73 +62 + 12 = 74 +62 + 13 = 75 +62 + 14 = 76 +62 + 15 = 77 +62 + 16 = 78 +62 + 17 = 79 +62 + 18 = 80 +62 + 19 = 81 +62 + 20 = 82 +62 + 21 = 83 +62 + 22 = 84 +62 + 23 = 85 +62 + 24 = 86 +62 + 25 = 87 +62 + 26 = 88 +62 + 27 = 89 +62 + 28 = 90 +62 + 29 = 91 +62 + 30 = 92 +62 + 31 = 93 +62 + 32 = 94 +62 + 33 = 95 +62 + 34 = 96 +62 + 35 = 97 +62 + 36 = 98 +62 + 37 = 99 +62 + 38 = 100 +62 + 39 = 101 +62 + 40 = 102 +62 + 41 = 103 +62 + 42 = 104 +62 + 43 = 105 +62 + 44 = 106 +62 + 45 = 107 +62 + 46 = 108 +62 + 47 = 109 +62 + 48 = 110 +62 + 49 = 111 +62 + 50 = 112 +62 + 51 = 113 +62 + 52 = 114 +62 + 53 = 115 +62 + 54 = 116 +62 + 55 = 117 +62 + 56 = 118 +62 + 57 = 119 +62 + 58 = 120 +62 + 59 = 121 +62 + 60 = 122 +62 + 61 = 123 +62 + 62 = 124 +62 + 63 = 125 +63 + 0 = 63 +63 + 1 = 64 +63 + 2 = 65 +63 + 3 = 66 +63 + 4 = 67 +63 + 5 = 68 +63 + 6 = 69 +63 + 7 = 70 +63 + 8 = 71 +63 + 9 = 72 +63 + 10 = 73 +63 + 11 = 74 +63 + 12 = 75 +63 + 13 = 76 +63 + 14 = 77 +63 + 15 = 78 +63 + 16 = 79 +63 + 17 = 80 +63 + 18 = 81 +63 + 19 = 82 +63 + 20 = 83 +63 + 21 = 84 +63 + 22 = 85 +63 + 23 = 86 +63 + 24 = 87 +63 + 25 = 88 +63 + 26 = 89 +63 + 27 = 90 +63 + 28 = 91 +63 + 29 = 92 +63 + 30 = 93 +63 + 31 = 94 +63 + 32 = 95 +63 + 33 = 96 +63 + 34 = 97 +63 + 35 = 98 +63 + 36 = 99 +63 + 37 = 100 +63 + 38 = 101 +63 + 39 = 102 +63 + 40 = 103 +63 + 41 = 104 +63 + 42 = 105 +63 + 43 = 106 +63 + 44 = 107 +63 + 45 = 108 +63 + 46 = 109 +63 + 47 = 110 +63 + 48 = 111 +63 + 49 = 112 +63 + 50 = 113 +63 + 51 = 114 +63 + 52 = 115 +63 + 53 = 116 +63 + 54 = 117 +63 + 55 = 118 +63 + 56 = 119 +63 + 57 = 120 +63 + 58 = 121 +63 + 59 = 122 +63 + 60 = 123 +63 + 61 = 124 +63 + 62 = 125 +63 + 63 = 126 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/main.cpp b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/main.cpp new file mode 100644 index 000000000..771aebbfa --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/main.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Main Filename: main.cc */ + /***************************************/ + /* */ + /* int = int + int */ + /* */ + /* Max addition is 63 + 63 */ + /* */ + /***************************************/ + +#include "datawidth.h" +#include "stimgen.h" + +int sc_main(int ac, char *av[]) +{ + +// Signal Instantiation + sc_signal in1 ("in1"); + sc_signal in2 ("in2"); + sc_signal result ("result"); + sc_signal ready ("ready"); + +// Clock Instantiation + sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS); + +// Process Instantiation + datawidth D1 ("D1", clk, in1, in2, ready, result); + + stimgen T1 ("T1", clk, result, in1, in2, ready); + +// Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.cpp b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.cpp new file mode 100644 index 000000000..ac55101ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimgen.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /*****************************************/ + /* Implementation Filename: stimgen.cc */ + /*****************************************/ + +#include "stimgen.h" + +void +stimgen::entry() +{ + int i; + int j; + + ready.write(0); + + for (i = 0; i < 64; i++) { // integer in1 (6 bits of data) + for (j = 0; j < 64; j++) { // integer in2 (6 bits of data) + in1.write(i); + in2.write(j); + ready.write(1); + wait(); + + ready.write(0); + wait(); + + cout << in1.read() << " + " << in2.read() + << " = " << result.read() << endl; + } + } + + sc_stop(); +} diff --git a/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.h b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.h new file mode 100644 index 000000000..479191043 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/datawidth_int_file/stimgen.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimgen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /************************************/ + /* Interface Filename: stimgen.h */ + /************************************/ + +#include "systemc.h" + +SC_MODULE( stimgen ) +{ + SC_HAS_PROCESS( stimgen ); + + sc_in_clk clk; + + // Inputs + const sc_signal& result; + // Outputs + sc_signal& in1; + sc_signal& in2; + sc_signal& ready; + + // Constructor + stimgen (sc_module_name NAME, + sc_clock& TICK, + const sc_signal& RESULT, + sc_signal& IN1, + sc_signal& IN2, + sc_signal& READY ) + + : + result (RESULT), + in1 (IN1), + in2 (IN2), + ready (READY) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/examples/parsing/activa.cpp b/src/systemc/tests/systemc/misc/examples/parsing/activa.cpp new file mode 100644 index 000000000..600884954 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/parsing/activa.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + activa.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( activa ) +{ + SC_HAS_PROCESS( activa ); + + sc_in_clk clk; + + const sc_signal& a; + const sc_signal& b; + sc_signal& c; + + activa( sc_module_name NAME, + sc_clock& CLK, + const sc_signal& A, + const sc_signal& B, + sc_signal& C ) + : + a(A), b(B), c(C) + { + clk( CLK ); + SC_CTHREAD( entry, clk.pos() ); + } + void entry(); +}; + +void activa::entry() +{ + bool cond1 = false, cond2 = false; + + while (1) { + c.write( a + b ); + if (cond1) { + if (cond2) { + c.write( a + b ); + } + c.write( a - b ); + } + c.write( a * b ); + } +} + +int +sc_main( int, char** ) +{ + sc_clock clk; + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/examples/parsing/golden/activa.log b/src/systemc/tests/systemc/misc/examples/parsing/golden/activa.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/examples/parsing/golden/activa.log @@ -0,0 +1 @@ +SystemC Simulation -- cgit v1.2.3