From e65a89e39b1c86e002e28a515508f5302a91a58f Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Mon, 11 Mar 2019 16:02:26 -0700
Subject: systemc: Create unified gem5/TLM bridge SimObjects.
These objects expose a standard TLM initiator or target socket with
width 64, and a gem5 slave or master port. What goes in one type of
port comes out the other with the appropriate conversion applied.
Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
---
src/systemc/tlm_bridge/TlmBridge.py | 52 +++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 src/systemc/tlm_bridge/TlmBridge.py
(limited to 'src/systemc/tlm_bridge/TlmBridge.py')
diff --git a/src/systemc/tlm_bridge/TlmBridge.py b/src/systemc/tlm_bridge/TlmBridge.py
new file mode 100644
index 000000000..d2dff8600
--- /dev/null
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -0,0 +1,52 @@
+# Copyright 2019 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.objects.SystemC import SystemC_ScModule
+from m5.params import *
+from m5.proxy import *
+
+class Gem5ToTlmBridge(SystemC_ScModule):
+ type = 'Gem5ToTlmBridge'
+ cxx_class = 'sc_gem5::Gem5ToTlmBridge'
+ cxx_header = 'systemc/tlm_bridge/gem5_to_tlm.hh'
+
+ system = Param.System(Parent.any, "system")
+
+ gem5 = SlavePort('gem5 slave port')
+ tlm = MasterPort('TLM initiator socket')
+ addr_ranges = VectorParam.AddrRange([],
+ 'Addresses served by this port\'s TLM side')
+
+class TlmToGem5Bridge(SystemC_ScModule):
+ type = 'TlmToGem5Bridge'
+ cxx_class = 'sc_gem5::TlmToGem5Bridge'
+ cxx_header = 'systemc/tlm_bridge/tlm_to_gem5.hh'
+
+ system = Param.System(Parent.any, "system")
+
+ gem5 = MasterPort('gem5 master port')
+ tlm = SlavePort('TLM target socket')
--
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