From 8561c8366c7c9afd7e6b52b6e2385b3c1dde95a9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 25 Jan 2007 13:43:46 -0500 Subject: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4 --- src/arch/sparc/isa/decoder.isa | 64 +++++++++++++++-------------- src/arch/sparc/isa/formats/mem/blockmem.isa | 6 +-- src/arch/sparc/isa/includes.isa | 3 +- src/arch/sparc/tlb.cc | 7 +++- src/arch/sparc/tlb_map.hh | 13 ++++++ src/cpu/simple/base.cc | 2 + 6 files changed, 58 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 548953982..425ebc9d0 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -186,7 +186,7 @@ decode OP default Unknown::unknown() Y = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; + Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); @@ -209,10 +209,10 @@ decode OP default Unknown::unknown() else { Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; - if(Rd.udw<63:31> != 0) + if((int64_t)Rd.udw >= std::numeric_limits::max()) Rd.udw = 0x7FFFFFFF; - else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) - Rd.udw = 0xFFFFFFFF80000000ULL; + else if((int64_t)Rd.udw <= std::numeric_limits::min()) + Rd.udw = ULL(0xFFFFFFFF80000000); } }}); } @@ -257,7 +257,7 @@ decode OP default Unknown::unknown() {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ int64_t resTemp; - Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; + Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ @@ -296,10 +296,10 @@ decode OP default Unknown::unknown() else { Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; - overflow = (Rd<63:31> != 0); - underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); + overflow = ((int64_t)Rd >= std::numeric_limits::max()); + underflow = ((int64_t)Rd <= std::numeric_limits::min()); if(overflow) Rd = 0x7FFFFFFF; - else if(underflow) Rd = 0xFFFFFFFF80000000ULL; + else if(underflow) Rd = ULL(0xFFFFFFFF80000000); } }}, {{0}}, {{overflow || underflow}}, @@ -376,7 +376,7 @@ decode OP default Unknown::unknown() 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); } 0x28: decode RS1 { - 0x00: NoPriv::rdy({{Rd = Y;}}); + 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); @@ -526,7 +526,7 @@ decode OP default Unknown::unknown() 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); } 0x30: decode RD { - 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); + 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); //0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); @@ -882,7 +882,7 @@ decode OP default Unknown::unknown() else { if (Pstate<3:>) - (Rd = xc->readPC())<31:0>; + Rd = (xc->readPC())<31:0>; else Rd = xc->readPC(); NNPC = target; @@ -1058,13 +1058,14 @@ decode OP default Unknown::unknown() 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); } 0x0D: LoadStore::ldstub( - {{Rd = Mem.ub;}}, - {{Mem.ub = 0xFF;}}); + {{uReg0 = Mem.ub;}}, + {{Rd.ub = uReg0; + Mem.ub = 0xFF;}}); 0x0E: Store::stx({{Mem.udw = Rd}}); 0x0F: LoadStore::swap( - {{uReg0 = Rd.uw; - Rd.uw = Mem.uw;}}, - {{Mem.uw = uReg0;}}); + {{ uReg0 = Mem.uw}}, + {{ Mem.uw = Rd.uw; + Rd.uw = uReg0;}}); format LoadAlt { 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); @@ -1072,34 +1073,34 @@ decode OP default Unknown::unknown() 0x13: decode EXT_ASI { //ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_N 0x27: TwinLoad::ldtx_n( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; @@ -1120,13 +1121,14 @@ decode OP default Unknown::unknown() 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); } 0x1D: LoadStoreAlt::ldstuba( - {{Rd = Mem.ub;}}, - {{Mem.ub = 0xFF}}, {{EXT_ASI}}); + {{uReg0 = Mem.ub;}}, + {{Rd.ub = uReg0; + Mem.ub = 0xFF;}}, {{EXT_ASI}}); 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 0x1F: LoadStoreAlt::swapa( - {{uReg0 = Rd.uw; - Rd.uw = Mem.uw;}}, - {{Mem.uw = uReg0;}}, {{EXT_ASI}}); + {{ uReg0 = Mem.uw}}, + {{ Mem.uw = Rd.uw; + Rd.uw = uReg0;}}, {{EXT_ASI}}); format Trap { 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 0x21: decode X { diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 32421a75f..c36fede2e 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -476,7 +476,6 @@ let {{ faultCode = '' return (header_output, decoder_output, exec_output, decode_block) - def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2 + offset;' addrCalcImm = 'EA = Rs1 + imm + offset;' @@ -492,10 +491,11 @@ let {{ pcedCode = '' if (microPc == 1): flag_code = "flags[IsLastMicroOp] = true;" - pcedCode = matcher.sub("RdHigh", code) + pcedCode = "RdLow = uReg0;\n" + pcedCode += matcher.sub("RdHigh", code) else: flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" - pcedCode = matcher.sub("RdLow", code) + pcedCode = matcher.sub("uReg0", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, "fault_check": faultCode, "micro_pc": microPc, diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 624afb693..0c112d481 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -63,6 +63,7 @@ output exec {{ #if defined(linux) #include #endif +#include #include "arch/sparc/asi.hh" #include "cpu/base.hh" diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 0e59f3e15..bf57c894f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -170,8 +170,8 @@ insertAllLocked: freeList.remove(new_entry); if (new_entry->valid && new_entry->used) usedEntries--; - - lookupTable.erase(new_entry->range); + if (new_entry->valid) + lookupTable.erase(new_entry->range); DPRINTF(TLB, "Using entry: %#X\n", new_entry); @@ -582,6 +582,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", vaddr, size, asi); + if (lookupTable.size() != 64 - freeList.size()) + panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), + freeList.size()); if (asi == ASI_IMPLICIT) implicit = true; diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh index 688daf5b9..8285db939 100644 --- a/src/arch/sparc/tlb_map.hh +++ b/src/arch/sparc/tlb_map.hh @@ -135,6 +135,19 @@ class TlbMap { return tree.empty(); } + + void print() + { + iterator i; + i = tree.begin(); + while (i != tree.end()) { + std::cout << std::hex << i->first.va << " " << i->first.size << " " << + i->first.contextId << " " << i->first.partitionId << " " << + i->first.real << " " << i->second << std::endl; + i++; + } + } + }; }; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ddccc5a9b..14fefe103 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -439,6 +439,8 @@ BaseSimpleCPU::advancePC(Fault fault) if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); + thread->setMicroPC(0); + thread->setNextMicroPC(1); } else { //If we're at the last micro op for this instruction if (curStaticInst->isLastMicroOp()) { -- cgit v1.2.3 From 73dd0ea35716b90c8448d729273cc153888a223b Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 25 Jan 2007 14:59:41 -0500 Subject: Instead of passing an int to represent time between python and C++ pass the tuple of python's struct_time and interpret that. Fixes a problem where the local timezone leaked into the time calculation. Also fix things so that the unix, python, and RTC data sheets all get the right time. Provide both years since 1900 and BCD two digit year. Put the date back at 1/1/2006 for now. --HG-- extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7 --- src/dev/alpha/tsunami_io.cc | 82 +++++++++++++++++++++++++++++++++------- src/dev/alpha/tsunami_io.hh | 13 ++++++- src/python/m5/objects/Tsunami.py | 4 +- src/python/m5/params.py | 70 ++++++++++++++++++---------------- 4 files changed, 121 insertions(+), 48 deletions(-) (limited to 'src') diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc index 38986b77e..d701dc98f 100644 --- a/src/dev/alpha/tsunami_io.cc +++ b/src/dev/alpha/tsunami_io.cc @@ -57,25 +57,77 @@ using namespace std; //Should this be AlphaISA? using namespace TheISA; -TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, time_t t, Tick i) - : _name(n), event(tsunami, i), addr(0) +TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector &t, + bool bcd, Tick i) + : _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd) { memset(clock_data, 0, sizeof(clock_data)); stat_regA = RTCA_32768HZ | RTCA_1024HZ; stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR; + if (year_is_bcd) { + // The RTC uses BCD for the last two digits in the year. + // They python year is a full year. + int _year = t[0] % 100; + int tens = _year / 10; + int ones = _year % 10; + + year = (tens << 4) + ones; + } else { + // Even though the datasheet says that the year field should be + // interpreted as BCD, we just enter the number of years since + // 1900 since linux seems to be happy with that (and I believe + // that Tru64 was as well) + year = t[0] - 1900; + } + + mon = t[1]; + mday = t[2]; + hour = t[3]; + min = t[4]; + sec = t[5]; + + // wday is defined to be in the range from 1 - 7 with 1 being Sunday. + // the value coming from python is in the range from 0 - 6 with 0 being + // Monday. Fix that here. + wday = t[6] + 2; + if (wday > 7) + wday -= 7; + + DPRINTFN("Real-time clock set to %s", getDateString()); +} + +std::string +TsunamiIO::RTC::getDateString() +{ struct tm tm; - gmtime_r(&t, &tm); - sec = tm.tm_sec; - min = tm.tm_min; - hour = tm.tm_hour; - wday = tm.tm_wday + 1; - mday = tm.tm_mday; - mon = tm.tm_mon + 1; - year = tm.tm_year; + memset(&tm, 0, sizeof(tm)); + + if (year_is_bcd) { + // undo the BCD and conver to years since 1900 guessing that + // anything before 1970 is actually after 2000 + int _year = (year >> 4) * 10 + (year & 0xf); + if (_year < 70) + _year += 100; + + tm.tm_year = _year; + } else { + // number of years since 1900 + tm.tm_year = year; + } + + // unix is 0-11 for month + tm.tm_mon = mon - 1; + tm.tm_mday = mday; + tm.tm_hour = hour; + tm.tm_min = min; + tm.tm_sec = sec; + + // to add more annoyance unix is 0 - 6 with 0 as sunday + tm.tm_wday = wday - 1; - DPRINTFN("Real-time clock set to %s", asctime(&tm)); + return asctime(&tm); } void @@ -424,7 +476,8 @@ TsunamiIO::PITimer::Counter::CounterEvent::description() TsunamiIO::TsunamiIO(Params *p) : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"), - rtc(p->name + ".rtc", p->tsunami, p->init_time, p->frequency) + rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd, + p->frequency) { pioSize = 0x100; @@ -649,7 +702,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) Param frequency; SimObjectParam platform; SimObjectParam system; - Param time; + VectorParam time; + Param year_is_bcd; SimObjectParam tsunami; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO) @@ -662,6 +716,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO) INIT_PARAM(platform, "platform"), INIT_PARAM(system, "system object"), INIT_PARAM(time, "System time to use (0 for actual time"), + INIT_PARAM(year_is_bcd, ""), INIT_PARAM(tsunami, "Tsunami") END_INIT_SIM_OBJECT_PARAMS(TsunamiIO) @@ -676,6 +731,7 @@ CREATE_SIM_OBJECT(TsunamiIO) p->platform = platform; p->system = system; p->init_time = time; + p->year_is_bcd = year_is_bcd; p->tsunami = tsunami; return new TsunamiIO(p); } diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index b0c368eb8..f42af4197 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -85,6 +85,9 @@ class TsunamiIO : public BasicPioDevice /** Current RTC register address/index */ int addr; + /** should the year be interpreted as BCD? */ + bool year_is_bcd; + /** Data for real-time clock function */ union { uint8_t clock_data[10]; @@ -110,7 +113,8 @@ class TsunamiIO : public BasicPioDevice uint8_t stat_regB; public: - RTC(const std::string &name, Tsunami* tsunami, time_t t, Tick i); + RTC(const std::string &name, Tsunami* tsunami, + const std::vector &t, bool bcd, Tick i); /** RTC address port: write address of RTC RAM data to access */ void writeAddr(const uint8_t data); @@ -121,6 +125,9 @@ class TsunamiIO : public BasicPioDevice /** RTC read data */ uint8_t readData(); + /** RTC get the date */ + std::string getDateString(); + /** * Serialize this object to the given output stream. * @param base The base name of the counter object. @@ -313,8 +320,10 @@ class TsunamiIO : public BasicPioDevice { Tick frequency; Tsunami *tsunami; - time_t init_time; + std::vector init_time; + bool year_is_bcd; }; + protected: const Params *params() const { return (const Params*)_params; } diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 18a776a7f..3d8e6dd04 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -13,8 +13,10 @@ class TsunamiCChip(BasicPioDevice): class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' - time = Param.Time('01/01/2009', + time = Param.Time('01/01/2006', "System time to use ('Now' for actual time)") + year_is_bcd = Param.Bool(False, + "The RTC should interpret the year as a BCD value") tsunami = Param.Tsunami(Parent.any, "Tsunami") frequency = Param.Frequency('1024Hz', "frequency of interrupts") diff --git a/src/python/m5/params.py b/src/python/m5/params.py index d570804d8..f8a9f9ddd 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -518,49 +518,55 @@ class EthernetAddr(ParamValue): else: return self.value +time_formats = [ "%a %b %d %H:%M:%S %Z %Y", + "%a %b %d %H:%M:%S %Z %Y", + "%Y/%m/%d %H:%M:%S", + "%Y/%m/%d %H:%M", + "%Y/%m/%d", + "%m/%d/%Y %H:%M:%S", + "%m/%d/%Y %H:%M", + "%m/%d/%Y", + "%m/%d/%y %H:%M:%S", + "%m/%d/%y %H:%M", + "%m/%d/%y"] + + def parse_time(value): - strings = [ "%a %b %d %H:%M:%S %Z %Y", - "%a %b %d %H:%M:%S %Z %Y", - "%Y/%m/%d %H:%M:%S", - "%Y/%m/%d %H:%M", - "%Y/%m/%d", - "%m/%d/%Y %H:%M:%S", - "%m/%d/%Y %H:%M", - "%m/%d/%Y", - "%m/%d/%y %H:%M:%S", - "%m/%d/%y %H:%M", - "%m/%d/%y"] - - for string in strings: - try: - return time.strptime(value, string) - except ValueError: - pass + from time import gmtime, strptime, struct_time, time + from datetime import datetime, date + + if isinstance(value, struct_time): + return value + + if isinstance(value, (int, long)): + return gmtime(value) + + if isinstance(value, (datetime, date)): + return value.timetuple() + + if isinstance(value, str): + if value in ('Now', 'Today'): + return time.gmtime(time.time()) + + for format in time_formats: + try: + return strptime(value, format) + except ValueError: + pass raise ValueError, "Could not parse '%s' as a time" % value class Time(ParamValue): cxx_type = 'time_t' def __init__(self, value): - if isinstance(value, time.struct_time): - self.value = time.mktime(value) - elif isinstance(value, int): - self.value = value - elif isinstance(value, str): - if value in ('Now', 'Today'): - self.value = time.time() - else: - self.value = time.mktime(parse_time(value)) - elif isinstance(value, (datetime.datetime, datetime.date)): - self.value = time.mktime(value.timetuple()) - else: - raise ValueError, "Could not parse '%s' as a time" % value + self.value = parse_time(value) def __str__(self): - return str(int(self.value)) + tm = self.value + return ' '.join([ str(tm[i]) for i in xrange(8)]) def ini_str(self): - return str(int(self.value)) + return str(self) # Enumerated types are a little more complex. The user specifies the # type as Enum(foo) where foo is either a list or dictionary of -- cgit v1.2.3 From cf7294250669e098e4ca47629afbbc6b52b6fb4c Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 25 Jan 2007 19:14:05 -0500 Subject: Move time forward to Jan 1, 2009 and update stats --HG-- extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea --- src/python/m5/objects/Tsunami.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 3d8e6dd04..85105ff20 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -13,7 +13,7 @@ class TsunamiCChip(BasicPioDevice): class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' - time = Param.Time('01/01/2006', + time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") year_is_bcd = Param.Bool(False, "The RTC should interpret the year as a BCD value") -- cgit v1.2.3 From 202d7f62b9ea11e6b72c4b15ff818549ea14f038 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 26 Jan 2007 12:51:07 -0500 Subject: eliminate cpu checkInterrupts bool, it is redundant and unnecessary. --HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719 --- src/arch/alpha/ev5.cc | 4 ---- src/arch/sparc/ua2005.cc | 11 +---------- src/cpu/base.cc | 4 +--- src/cpu/base.hh | 1 - src/cpu/o3/alpha/cpu_impl.hh | 3 --- src/cpu/o3/commit_impl.hh | 3 +-- src/cpu/o3/sparc/cpu_impl.hh | 1 - src/cpu/ozone/cpu_impl.hh | 7 ------- src/cpu/ozone/inorder_back_end_impl.hh | 4 +--- src/cpu/simple/base.cc | 3 +-- 10 files changed, 5 insertions(+), 36 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 3d71fbda5..8d13511ac 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -94,8 +94,6 @@ AlphaISA::processInterrupts(CPU *cpu) int ipl = 0; int summary = 0; - cpu->checkInterrupts = false; - if (cpu->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); @@ -155,8 +153,6 @@ SimpleThread::hwrei() if (!misspeculating()) { if (kernelStats) kernelStats->hwrei(); - - cpu->checkInterrupts = true; } // FIXME: XXX check for interrupts? XXX diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 6220e6dec..b583da8b0 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -50,7 +50,6 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_SOFTINT_CLR: return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - tc->getCpuPtr()->checkInterrupts = true; tc->getCpuPtr()->post_interrupt(soft_interrupt); return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); @@ -80,15 +79,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_PSTATE: - if (val & PSTATE::ie && !(pstate & PSTATE::ie)) { - tc->getCpuPtr()->checkInterrupts = true; - } setReg(miscReg, val); case MISCREG_PIL: - if (val < pil) { - tc->getCpuPtr()->checkInterrupts = true; - } setReg(miscReg, val); break; @@ -112,7 +105,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: setReg(miscReg, val); - tc->getCpuPtr()->checkInterrupts = true; + //do something to post mondo interrupt break; case MISCREG_HSTICK_CMPR: @@ -208,7 +201,6 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) (stick_cmpr & mask(63))); if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { tc->getCpuPtr()->post_interrupt(soft_interrupt); - tc->getCpuPtr()->checkInterrupts = true; setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else @@ -232,7 +224,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { setRegWithEffect(MISCREG_HINTP, 1, tc); tc->getCpuPtr()->post_interrupt(hstick_match); - tc->getCpuPtr()->checkInterrupts = true; } // Need to do something to cause interrupt to happen here !!! @todo } else diff --git a/src/cpu/base.cc b/src/cpu/base.cc index b03bc19a5..deb4e02c4 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -96,7 +96,7 @@ CPUProgressEvent::description() #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true), + : MemObject(p->name), clock(p->clock), instCnt(0), params(p), number_of_threads(p->numberOfThreads), system(p->system), phase(p->phase) #else @@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) #if FULL_SYSTEM interrupts = oldCPU->interrupts; - checkInterrupts = oldCPU->checkInterrupts; for (int i = 0; i < threadContexts.size(); ++i) threadContexts[i]->profileClear(); @@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type) void BaseCPU::post_interrupt(int int_num, int index) { - checkInterrupts = true; interrupts.post(int_num, index); } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 89c7d9dda..3ae9c60b6 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -106,7 +106,6 @@ class BaseCPU : public MemObject virtual void post_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupts(); - bool checkInterrupts; bool check_interrupts(ThreadContext * tc) const { return interrupts.check_interrupts(tc); } diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 98fd0699a..980e70fdd 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -217,8 +217,6 @@ AlphaO3CPU::hwrei(unsigned tid) this->thread[tid]->kernelStats->hwrei(); - this->checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -270,7 +268,6 @@ AlphaO3CPU::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 96f094926..483c2f71b 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -671,8 +671,7 @@ DefaultCommit::commit() } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } - } else if (cpu->checkInterrupts && - cpu->check_interrupts(cpu->tcBase(0)) && + } else if (cpu->check_interrupts(cpu->tcBase(0)) && commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 536a620bf..66bf7d1c0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -245,7 +245,6 @@ SparcO3CPU::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index accc8d294..a854de8de 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -182,10 +182,6 @@ OzoneCPU::OzoneCPU(Params *p) globalSeqNum = 1; -#if FULL_SYSTEM - checkInterrupts = false; -#endif - lockFlag = 0; // Setup rename table, initializing all values to ready. @@ -684,8 +680,6 @@ OzoneCPU::hwrei() lockAddrList.clear(); thread.kernelStats->hwrei(); - checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -704,7 +698,6 @@ OzoneCPU::processInterrupts() if (interrupt != NoFault) { this->interrupts.updateIntrInfo(thread.getTC()); - this->checkInterrupts = false; interrupt->invoke(thread.getTC()); } } diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 87bf0a7a2..84f935a72 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -88,7 +88,6 @@ InorderBackEnd::checkInterrupts() int ipl = 0; int summary = 0; - cpu->checkInterrupts = false; if (thread->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); @@ -151,8 +150,7 @@ InorderBackEnd::tick() // I'm waiting for it to drain. (for now just squash) #if FULL_SYSTEM if (interruptBlocked || - (cpu->checkInterrupts && - cpu->check_interrupts(tc))) { + cpu->check_interrupts(tc)) { if (!robEmpty()) { interruptBlocked = true; //AlphaDep diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ddccc5a9b..9e5dfe2a6 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -311,12 +311,11 @@ void BaseSimpleCPU::checkForInterrupts() { #if FULL_SYSTEM - if (checkInterrupts && check_interrupts(tc)) { + if (check_interrupts(tc)) { Fault interrupt = interrupts.getInterrupt(tc); if (interrupt != NoFault) { interrupts.updateIntrInfo(tc); - checkInterrupts = false; interrupt->invoke(tc); } } -- cgit v1.2.3 From 63fdabf191b8ac1031fb25da61ab2526d4bb6d05 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:48:51 -0500 Subject: make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd --- src/SConscript | 29 +++++++++++++------- src/arch/sparc/isa/decoder.isa | 4 +-- src/arch/sparc/isa/formats/basic.isa | 3 ++- src/arch/sparc/isa/formats/integerop.isa | 6 ++--- src/arch/sparc/isa/includes.isa | 4 ++- src/arch/sparc/isa_traits.hh | 2 +- src/arch/sparc/system.cc | 1 + src/arch/sparc/tlb.cc | 4 ++- src/arch/sparc/utility.hh | 2 +- src/base/compression/lzss_compression.cc | 6 ++--- src/base/compression/null_compression.hh | 2 ++ src/base/cprintf.hh | 24 ++++++++--------- src/base/hashmap.hh | 2 +- src/base/hostinfo.cc | 1 + src/base/loader/object_file.cc | 4 +-- src/base/misc.hh | 45 ++++++++++++++++++-------------- src/base/pollevent.cc | 2 +- src/base/random.cc | 13 ++++++--- src/base/remote_gdb.cc | 5 +++- src/base/statistics.hh | 5 +++- src/base/stats/text.cc | 4 +++ src/base/time.cc | 4 +++ src/base/time.hh | 2 +- src/base/timebuf.hh | 5 ++-- src/base/trace.hh | 28 ++++++++++---------- src/cpu/SConscript | 8 +++--- src/cpu/activity.cc | 6 +++-- src/cpu/exetrace.hh | 3 ++- src/cpu/simple/base.hh | 3 ++- src/dev/baddev.cc | 2 ++ src/dev/ide_atareg.h | 2 +- src/dev/io_device.hh | 2 +- src/dev/pciconfigall.cc | 2 ++ src/dev/pcidev.hh | 6 +++-- src/dev/platform.cc | 1 + src/dev/sparc/mm_disk.cc | 5 +++- src/dev/sparc/t1000.cc | 3 +++ src/mem/cache/cache_impl.hh | 31 +++++++++++----------- src/mem/cache/miss/blocking_buffer.cc | 9 ++++--- src/mem/cache/miss/blocking_buffer.hh | 2 ++ src/mem/cache/tags/iic.cc | 2 +- src/mem/cache/tags/lru.hh | 3 ++- src/mem/cache/tags/split.hh | 4 ++- src/mem/cache/tags/split_lifo.hh | 3 ++- src/mem/cache/tags/split_lru.hh | 3 ++- src/mem/dram.cc | 4 +-- src/mem/packet.cc | 8 +++--- src/mem/physical.cc | 6 ++--- src/mem/port.cc | 3 ++- src/mem/port.hh | 8 +++--- src/sim/byteswap.hh | 2 +- 51 files changed, 207 insertions(+), 131 deletions(-) (limited to 'src') diff --git a/src/SConscript b/src/SConscript index 229418703..a94682bc0 100644 --- a/src/SConscript +++ b/src/SConscript @@ -311,30 +311,41 @@ def makeEnv(label, objsfx, strip = False, **kwargs): envList.append(newEnv) # Debug binary -# Solaris seems to have some issue with DWARF2 debugging information, it's ok -# with stabs though -if sys.platform == 'sunos5': - debug_flag = '-gstabs+' +ccflags = {} +if env['GCC']: + if sys.platform == 'sunos5': + ccflags['debug'] = '-gstabs+' + else: + ccflags['debug'] = '-ggdb3' + ccflags['opt'] = '-g -O3' + ccflags['fast'] = '-O3' + ccflags['prof'] = '-O3 -g -pg' +elif env['SUNCC']: + ccflags['debug'] = '-g0' + ccflags['opt'] = '-g -O' + ccflags['fast'] = '-fast' + ccflags['prof'] = '-fast -g -pg' else: - debug_flag = '-ggdb3' + print 'Unknown compiler, please fix compiler options' + Exit(1) makeEnv('debug', '.do', - CCFLAGS = Split('%s -O0' % debug_flag), + CCFLAGS = Split(ccflags['debug']), CPPDEFINES = ['DEBUG', 'TRACING_ON=1']) # Optimized binary makeEnv('opt', '.o', - CCFLAGS = Split('-g -O3'), + CCFLAGS = Split(ccflags['opt']), CPPDEFINES = ['TRACING_ON=1']) # "Fast" binary makeEnv('fast', '.fo', strip = True, - CCFLAGS = Split('-O3'), + CCFLAGS = Split(ccflags['fast']), CPPDEFINES = ['NDEBUG', 'TRACING_ON=0']) # Profiled binary makeEnv('prof', '.po', - CCFLAGS = Split('-O3 -g -pg'), + CCFLAGS = Split(ccflags['prof']), CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'], LINKFLAGS = '-pg') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index bd1a44342..bfb8252b9 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -685,8 +685,8 @@ decode OP default Unknown::unknown() Fsr &= ~(0x1F); }}); 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); - 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); - 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); + 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); + 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a4c05387b..9805c7c0b 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -38,6 +38,7 @@ def template BasicExecPanic {{ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); + M5_DUMMY_RETURN } }}; diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 4f8ebebcc..9470fc55f 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -154,7 +154,7 @@ output decoder {{ bool IntOp::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) + if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) { printMnemonic(os, "mov"); printSrcReg(os, 1); @@ -168,7 +168,7 @@ output decoder {{ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or")) + if(!std::strcmp(mnemonic, "or")) { if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) { diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 624afb693..688f26d5c 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -34,6 +34,7 @@ // output header {{ +#include #include #include @@ -64,6 +65,7 @@ output exec {{ #include #endif +#include #include "arch/sparc/asi.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 3f0b9cad5..ea15fac10 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -59,7 +59,7 @@ namespace SparcISA // These enumerate all the registers for dependence tracking. enum DependenceTags { FP_Base_DepTag = 33, - Ctrl_Base_DepTag = 97, + Ctrl_Base_DepTag = 97 }; // semantically meaningful register indices diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index da83d86fc..800d47c15 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -195,6 +195,7 @@ bool SparcSystem::breakpoint() { panic("Need to implement"); + M5_DUMMY_RETURN } void diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 612345300..dc4c9ef1f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -28,6 +28,8 @@ * Authors: Ali Saidi */ +#include + #include "arch/sparc/asi.hh" #include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" @@ -53,7 +55,7 @@ TLB::TLB(const std::string &name, int s) fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); tlb = new TlbEntry[size]; - memset(tlb, 0, sizeof(TlbEntry) * size); + std::memset(tlb, 0, sizeof(TlbEntry) * size); for (int x = 0; x < size; x++) freeList.push_back(&tlb[x]); diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 5c7fe343d..3c8bdcd01 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -50,7 +50,7 @@ namespace SparcISA inline ExtMachInst makeExtMI(MachInst inst, ThreadContext * xc) { - ExtMachInst emi = (unsigned MachInst) inst; + ExtMachInst emi = (MachInst) inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is //slightly redundant, but it removes the need to put a condition diff --git a/src/base/compression/lzss_compression.cc b/src/base/compression/lzss_compression.cc index eb35fb8f1..bd16d82c9 100644 --- a/src/base/compression/lzss_compression.cc +++ b/src/base/compression/lzss_compression.cc @@ -32,8 +32,8 @@ * LZSSCompression definitions. */ -#include - +#include +#include #include "base/compression/lzss_compression.hh" #include "base/misc.hh" //for fatal @@ -134,7 +134,7 @@ LZSSCompression::compress(uint8_t *dest, uint8_t *src, int size) if (dest_index >= size) { // Have expansion instead of compression, just copy. - memcpy(dest,src,size); + std::memcpy(dest,src,size); return size; } return dest_index; diff --git a/src/base/compression/null_compression.hh b/src/base/compression/null_compression.hh index ff110807a..798acb77a 100644 --- a/src/base/compression/null_compression.hh +++ b/src/base/compression/null_compression.hh @@ -50,11 +50,13 @@ class NullCompression : public CompressionAlgorithm int uncompress(uint8_t * dest, uint8_t *src, int size) { fatal("Can't uncompress data"); + M5_DUMMY_RETURN } int compress(uint8_t *dest, uint8_t *src, int size) { fatal("Can't compress data"); + M5_DUMMY_RETURN } }; diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh index 9967b0578..dd2256e69 100644 --- a/src/base/cprintf.hh +++ b/src/base/cprintf.hh @@ -136,10 +136,10 @@ operator,(ArgList &alist, ArgListNull) inline void __cprintf(const std::string &format, ArgList &args) { args.dump(format); delete &args; } -#define __cprintf__(format, args...) \ - cp::__cprintf(format, (*(new cp::ArgList), args)) -#define cprintf(args...) \ - __cprintf__(args, cp::ArgListNull()) +#define __cprintf__(format, ...) \ + cp::__cprintf(format, (*(new cp::ArgList), __VA_ARGS__)) +#define cprintf(...) \ + __cprintf__(__VA_ARGS__, cp::ArgListNull()) // // ccprintf(stream, format, args, ...) prints to the specified stream @@ -148,10 +148,10 @@ __cprintf(const std::string &format, ArgList &args) inline void __ccprintf(std::ostream &stream, const std::string &format, ArgList &args) { args.dump(stream, format); delete &args; } -#define __ccprintf__(stream, format, args...) \ - cp::__ccprintf(stream, format, (*(new cp::ArgList), args)) -#define ccprintf(stream, args...) \ - __ccprintf__(stream, args, cp::ArgListNull()) +#define __ccprintf__(stream, format, ...) \ + cp::__ccprintf(stream, format, (*(new cp::ArgList), __VA_ARGS__)) +#define ccprintf(stream, ...) \ + __ccprintf__(stream, __VA_ARGS__, cp::ArgListNull()) // // csprintf(format, args, ...) returns a string @@ -160,10 +160,10 @@ __ccprintf(std::ostream &stream, const std::string &format, ArgList &args) inline std::string __csprintf(const std::string &format, ArgList &args) { std::string s = args.dumpToString(format); delete &args; return s; } -#define __csprintf__(format, args...) \ - cp::__csprintf(format, (*(new cp::ArgList), args)) -#define csprintf(args...) \ - __csprintf__(args, cp::ArgListNull()) +#define __csprintf__(format, ...) \ + cp::__csprintf(format, (*(new cp::ArgList), __VA_ARGS__)) +#define csprintf(...) \ + __csprintf__(__VA_ARGS__, cp::ArgListNull()) } diff --git a/src/base/hashmap.hh b/src/base/hashmap.hh index 570cbc152..b78cc02e8 100644 --- a/src/base/hashmap.hh +++ b/src/base/hashmap.hh @@ -59,7 +59,7 @@ namespace m5 { // namespace __hash_namespace { -#if !defined(__LP64__) && !defined(__alpha__) +#if !defined(__LP64__) && !defined(__alpha__) && !defined(__SUNPRO_CC) template<> struct hash { size_t operator()(uint64_t r) const { diff --git a/src/base/hostinfo.cc b/src/base/hostinfo.cc index a7c93e712..7cc07c11e 100644 --- a/src/base/hostinfo.cc +++ b/src/base/hostinfo.cc @@ -33,6 +33,7 @@ #include #include +#include #include #include #include diff --git a/src/base/loader/object_file.cc b/src/base/loader/object_file.cc index ad2cd34ba..2273b6c4e 100644 --- a/src/base/loader/object_file.cc +++ b/src/base/loader/object_file.cc @@ -101,7 +101,7 @@ ObjectFile::close() } if (fileData) { - ::munmap(fileData, len); + ::munmap((char*)fileData, len); fileData = NULL; } } @@ -147,6 +147,6 @@ createObjectFile(const string &fname, bool raw) // don't know what it is close(fd); - munmap(fileData, len); + munmap((char*)fileData, len); return NULL; } diff --git a/src/base/misc.hh b/src/base/misc.hh index 1c5720ce1..c12c2fe20 100644 --- a/src/base/misc.hh +++ b/src/base/misc.hh @@ -33,8 +33,13 @@ #define __MISC_HH__ #include +#include "base/compiler.hh" #include "base/cprintf.hh" +#if defined(__SUNPRO_CC) +#define __FUNCTION__ "how to fix me?" +#endif + // // This implements a cprintf based panic() function. panic() should // be called when something happens that should never ever happen @@ -43,12 +48,13 @@ // // void __panic(const std::string&, cp::ArgList &, const char*, const char*, int) - __attribute__((noreturn)); -#define __panic__(format, args...) \ - __panic(format, (*(new cp::ArgList), args), \ - __FUNCTION__, __FILE__, __LINE__) -#define panic(args...) \ - __panic__(args, cp::ArgListNull()) + M5_ATTR_NORETURN; +#define __panic__(format, ...) \ + __panic(format, (*(new cp::ArgList), __VA_ARGS__), \ + __FUNCTION__ , __FILE__, __LINE__) +#define panic(...) \ + __panic__(__VA_ARGS__, cp::ArgListNull()) +M5_PRAGMA_NORETURN(__panic) // // This implements a cprintf based fatal() function. fatal() should @@ -59,32 +65,33 @@ void __panic(const std::string&, cp::ArgList &, const char*, const char*, int) // panic() does. // void __fatal(const std::string&, cp::ArgList &, const char*, const char*, int) - __attribute__((noreturn)); -#define __fatal__(format, args...) \ - __fatal(format, (*(new cp::ArgList), args), \ - __FUNCTION__, __FILE__, __LINE__) -#define fatal(args...) \ - __fatal__(args, cp::ArgListNull()) + M5_ATTR_NORETURN; +#define __fatal__(format, ...) \ + __fatal(format, (*(new cp::ArgList), __VA_ARGS__), \ + __FUNCTION__ , __FILE__, __LINE__) +#define fatal(...) \ + __fatal__(__VA_ARGS__, cp::ArgListNull()) +M5_PRAGMA_NORETURN(__fatal) // // This implements a cprintf based warn // void __warn(const std::string&, cp::ArgList &, const char*, const char*, int); -#define __warn__(format, args...) \ - __warn(format, (*(new cp::ArgList), args), \ - __FUNCTION__, __FILE__, __LINE__) -#define warn(args...) \ - __warn__(args, cp::ArgListNull()) +#define __warn__(format, ...) \ + __warn(format, (*(new cp::ArgList), __VA_ARGS__), \ + __FUNCTION__ , __FILE__, __LINE__) +#define warn(...) \ + __warn__(__VA_ARGS__, cp::ArgListNull()) // Only print the warning message the first time it is seen. This // doesn't check the warning string itself, it just only lets one // warning come from the statement. So, even if the arguments change // and that would have resulted in a different warning message, // subsequent messages would still be supressed. -#define warn_once(args...) do { \ +#define warn_once(...) do { \ static bool once = false; \ if (!once) { \ - __warn__(args, cp::ArgListNull()); \ + __warn__(__VA_ARGS__, cp::ArgListNull()); \ once = true; \ } \ } while (0) diff --git a/src/base/pollevent.cc b/src/base/pollevent.cc index fd5b09d28..32724b74d 100644 --- a/src/base/pollevent.cc +++ b/src/base/pollevent.cc @@ -30,7 +30,7 @@ #include #include -#if defined(__sun__) +#if defined(__sun__) || defined(__SUNPRO_CC) #include #endif diff --git a/src/base/random.cc b/src/base/random.cc index 82c9e3566..0ccedcb00 100644 --- a/src/base/random.cc +++ b/src/base/random.cc @@ -29,12 +29,17 @@ * Ali Saidi */ +#if defined(__sun) +#include +#endif +#ifdef __SUNPRO_CC +#include +#include +#endif + #include #include -#if defined(__sun__) -#include -#endif #include "sim/param.hh" #include "base/random.hh" @@ -72,7 +77,7 @@ getLong() double m5round(double r) { -#if defined(__sun__) +#if defined(__sun) double val; fp_rnd oldrnd = fpsetround(FP_RN); val = rint(r); diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index 59a9b87d5..2c0da48f0 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -610,7 +610,7 @@ BaseRemoteGDB::trap(int type) uint64_t val; size_t datalen, len; char data[GDBPacketBufLen + 1]; - char buffer[gdbregs.bytes() * 2 + 256]; + char *buffer; const char *p; char command, subcmd; string var; @@ -619,6 +619,8 @@ BaseRemoteGDB::trap(int type) if (!attached) return false; + buffer = (char*)malloc(gdbregs.bytes() * 2 + 256); + DPRINTF(GDBMisc, "trap: PC=%#x NPC=%#x\n", context->readPC(), context->readNextPC()); @@ -916,6 +918,7 @@ BaseRemoteGDB::trap(int type) } out: + free(buffer); return true; } diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 577ea5eab..d8e8b4c15 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -50,6 +50,9 @@ #include #include +#ifdef __SUNPRO_CC +#include +#endif #include #include #include @@ -1410,7 +1413,7 @@ struct DistStor else if (val > params.max) overflow += number; else { - int index = (int)floor((val - params.min) / params.bucket_size); + int index = (int)std::floor((val - params.min) / params.bucket_size); assert(index < size(params)); cvec[index] += number; } diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc index c4448efc9..ae0d65537 100644 --- a/src/base/stats/text.cc +++ b/src/base/stats/text.cc @@ -32,6 +32,10 @@ #define _GLIBCPP_USE_C99 1 #endif +#if defined(__sun) +#include +#endif + #include #include #include diff --git a/src/base/time.cc b/src/base/time.cc index cbc7256ee..76ba355b7 100644 --- a/src/base/time.cc +++ b/src/base/time.cc @@ -105,7 +105,11 @@ Time::date(string format) const char buf[256]; if (format.empty()) { +#ifdef __SUNPRO_CC + ctime_r(&sec, buf, 256); +#else ctime_r(&sec, buf); +#endif buf[24] = '\0'; return buf; } diff --git a/src/base/time.hh b/src/base/time.hh index 7aa4c50db..f10cc5d6c 100644 --- a/src/base/time.hh +++ b/src/base/time.hh @@ -97,7 +97,7 @@ std::ostream &operator<<(std::ostream &out, const Time &time); * @(#)time.h 8.2 (Berkeley) 7/10/94 */ -#if defined(__sun__) +#if defined(__sun) #define timersub(tvp, uvp, vvp) \ do { \ (vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec; \ diff --git a/src/base/timebuf.hh b/src/base/timebuf.hh index 1d0de8278..348f7a673 100644 --- a/src/base/timebuf.hh +++ b/src/base/timebuf.hh @@ -33,6 +33,7 @@ #define __BASE_TIMEBUF_HH__ #include +#include #include template @@ -143,7 +144,7 @@ class TimeBuffer char *ptr = data; for (int i = 0; i < size; i++) { index[i] = ptr; - memset(ptr, 0, sizeof(T)); + std::memset(ptr, 0, sizeof(T)); new (ptr) T; ptr += sizeof(T); } @@ -171,7 +172,7 @@ class TimeBuffer if (ptr >= size) ptr -= size; (reinterpret_cast(index[ptr]))->~T(); - memset(index[ptr], 0, sizeof(T)); + std::memset(index[ptr], 0, sizeof(T)); new (index[ptr]) T; } diff --git a/src/base/trace.hh b/src/base/trace.hh index 9b053990c..a46643159 100644 --- a/src/base/trace.hh +++ b/src/base/trace.hh @@ -186,39 +186,39 @@ do { \ Trace::dataDump(curTick, name(), data, count); \ } while (0) -#define __dprintf(cycle, name, format, args...) \ - Trace::dprintf(format, (*(new cp::ArgList), args), cycle, name) +#define __dprintf(cycle, name, format, ...) \ + Trace::dprintf(format, (*(new cp::ArgList), __VA_ARGS__), cycle, name) -#define DPRINTF(x, args...) \ +#define DPRINTF(x, ...) \ do { \ if (Trace::IsOn(Trace::x)) \ - __dprintf(curTick, name(), args, cp::ArgListNull()); \ + __dprintf(curTick, name(), __VA_ARGS__, cp::ArgListNull()); \ } while (0) -#define DPRINTFR(x, args...) \ +#define DPRINTFR(x, ...) \ do { \ if (Trace::IsOn(Trace::x)) \ - __dprintf((Tick)-1, std::string(), args, cp::ArgListNull()); \ + __dprintf((Tick)-1, std::string(), __VA_ARGS__, cp::ArgListNull()); \ } while (0) -#define DPRINTFN(args...) \ +#define DPRINTFN(...) \ do { \ - __dprintf(curTick, name(), args, cp::ArgListNull()); \ + __dprintf(curTick, name(), __VA_ARGS__, cp::ArgListNull()); \ } while (0) -#define DPRINTFNR(args...) \ +#define DPRINTFNR(...) \ do { \ - __dprintf((Tick)-1, string(), args, cp::ArgListNull()); \ + __dprintf((Tick)-1, string(), __VA_ARGS__, cp::ArgListNull()); \ } while (0) #else // !TRACING_ON #define DTRACE(x) (false) #define DCOUT(x) if (0) DebugOut() -#define DPRINTF(x, args...) do {} while (0) -#define DPRINTFR(args...) do {} while (0) -#define DPRINTFN(args...) do {} while (0) -#define DPRINTFNR(args...) do {} while (0) +#define DPRINTF(x, ...) do {} while (0) +#define DPRINTFR(...) do {} while (0) +#define DPRINTFN(...) do {} while (0) +#define DPRINTFNR(...) do {} while (0) #define DDUMP(x, data, count) do {} while (0) #endif // TRACING_ON diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 5771a7904..4d4b7574c 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -54,18 +54,18 @@ execfile(models_db.srcnode().abspath) exec_sig_template = ''' virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const -{ panic("initiateAcc not defined!"); }; +{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; virtual Fault completeAcc(Packet *pkt, %s *xc, Trace::InstRecord *traceData) const -{ panic("completeAcc not defined!"); }; +{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; ''' mem_ini_sig_template = ''' -virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); }; +virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; ''' mem_comp_sig_template = ''' -virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; }; +virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; ''' # Generate a temporary CPU list, including the CheckerCPU if diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc index 9a0f6d98d..15e0556ad 100644 --- a/src/cpu/activity.cc +++ b/src/cpu/activity.cc @@ -28,6 +28,8 @@ * Authors: Kevin Lim */ +#include + #include "base/timebuf.hh" #include "cpu/activity.hh" @@ -37,7 +39,7 @@ ActivityRecorder::ActivityRecorder(int num_stages, int longest_latency, activityCount(activity), numStages(num_stages) { stageActive = new bool[numStages]; - memset(stageActive, 0, numStages); + std::memset(stageActive, 0, numStages); } void @@ -114,7 +116,7 @@ void ActivityRecorder::reset() { activityCount = 0; - memset(stageActive, 0, numStages); + std::memset(stageActive, 0, numStages); for (int i = 0; i < longestLatency + 1; ++i) activityBuffer.advance(); } diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index 6562e5265..a825f6a82 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -32,6 +32,7 @@ #ifndef __EXETRACE_HH__ #define __EXETRACE_HH__ +#include #include #include @@ -169,7 +170,7 @@ InstRecord::setRegs(const IntRegFile ®s) if (!iregs) iregs = new iRegFile; - memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); + std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); regs_valid = true; } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index c39bfa9cd..31fd00977 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -186,7 +186,8 @@ class BaseSimpleCPU : public BaseCPU // These functions are only used in CPU models that split // effective address computation from the actual memory access. void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } - Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } + Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); + M5_DUMMY_RETURN} void prefetch(Addr addr, unsigned flags) { diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc index 6a7060455..a2d2650cb 100644 --- a/src/dev/baddev.cc +++ b/src/dev/baddev.cc @@ -56,12 +56,14 @@ Tick BadDevice::read(PacketPtr pkt) { panic("Device %s not imlpmented\n", devname); + M5_DUMMY_RETURN } Tick BadDevice::write(PacketPtr pkt) { panic("Device %s not imlpmented\n", devname); + M5_DUMMY_RETURN } BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice) diff --git a/src/dev/ide_atareg.h b/src/dev/ide_atareg.h index df16d09d5..b9f1d9e0f 100644 --- a/src/dev/ide_atareg.h +++ b/src/dev/ide_atareg.h @@ -35,7 +35,7 @@ #if defined(linux) #include -#elif defined(__sun__) +#elif defined(__sun) #include #else #include diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index aa242d170..c56eba267 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -109,7 +109,7 @@ class DmaPort : public Port virtual bool recvTiming(PacketPtr pkt); virtual Tick recvAtomic(PacketPtr pkt) - { panic("dma port shouldn't be used for pio access."); } + { panic("dma port shouldn't be used for pio access."); M5_DUMMY_RETURN } virtual void recvFunctional(PacketPtr pkt) { panic("dma port shouldn't be used for pio access."); } diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc index 39c8f0fa0..bd1855847 100644 --- a/src/dev/pciconfigall.cc +++ b/src/dev/pciconfigall.cc @@ -83,8 +83,10 @@ PciConfigAll::write(PacketPtr pkt) { assert(pkt->result == Packet::Unknown); panic("Attempting to write to config space on non-existant device\n"); + M5_DUMMY_RETURN } + void PciConfigAll::addressRanges(AddrRangeList &range_list) { diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index fbfdbb65c..56e3ffb4a 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -37,6 +37,8 @@ #ifndef __DEV_PCIDEV_HH__ #define __DEV_PCIDEV_HH__ +#include + #include "dev/io_device.hh" #include "dev/pcireg.h" #include "dev/platform.hh" @@ -62,8 +64,8 @@ class PciConfigData : public SimObject PciConfigData(const std::string &name) : SimObject(name) { - memset(config.data, 0, sizeof(config.data)); - memset(BARSize, 0, sizeof(BARSize)); + std::memset(config.data, 0, sizeof(config.data)); + std::memset(BARSize, 0, sizeof(BARSize)); } /** The first 64 bytes */ diff --git a/src/dev/platform.cc b/src/dev/platform.cc index 07288249c..b2b8695a7 100644 --- a/src/dev/platform.cc +++ b/src/dev/platform.cc @@ -62,6 +62,7 @@ Addr Platform::pciToDma(Addr pciAddr) const { panic("No PCI dma support in platform."); + M5_DUMMY_RETURN } void diff --git a/src/dev/sparc/mm_disk.cc b/src/dev/sparc/mm_disk.cc index 9057c28be..018415f6c 100644 --- a/src/dev/sparc/mm_disk.cc +++ b/src/dev/sparc/mm_disk.cc @@ -33,6 +33,8 @@ * in legion. Any access is translated to an offset in the disk image. */ +#include + #include "base/trace.hh" #include "dev/sparc/mm_disk.hh" #include "dev/platform.hh" @@ -45,7 +47,7 @@ MmDisk::MmDisk(Params *p) : BasicPioDevice(p), image(p->image), curSector((uint64_t)-1), dirty(false) { - memset(&bytes, 0, SectorSize); + std::memset(&bytes, 0, SectorSize); pioSize = image->size() * SectorSize; } @@ -99,6 +101,7 @@ Tick MmDisk::write(PacketPtr pkt) { panic("need to implement\n"); + M5_DUMMY_RETURN } diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc index 4a8de77a5..233808631 100644 --- a/src/dev/sparc/t1000.cc +++ b/src/dev/sparc/t1000.cc @@ -57,6 +57,7 @@ Tick T1000::intrFrequency() { panic("Need implementation\n"); + M5_DUMMY_RETURN } void @@ -89,6 +90,7 @@ Addr T1000::pciToDma(Addr pciAddr) const { panic("Need implementation\n"); + M5_DUMMY_RETURN } @@ -96,6 +98,7 @@ Addr T1000::calcConfigAddr(int bus, int dev, int func) { panic("Need implementation\n"); + M5_DUMMY_RETURN } void diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 9c41983fc..b8c896498 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -40,6 +40,7 @@ #include #include +#include #include #include "sim/host.hh" @@ -125,7 +126,7 @@ Cache::handleAccess(PacketPtr &pkt, int & lat, assert(offset < blkSize); assert(pkt->getSize() <= blkSize); assert(offset+pkt->getSize() <= blkSize); - memcpy(blk->data + offset, pkt->getPtr(), + std::memcpy(blk->data + offset, pkt->getPtr(), pkt->getSize()); } else if (!(pkt->flags & SATISFIED)) { pkt->flags |= SATISFIED; @@ -133,7 +134,7 @@ Cache::handleAccess(PacketPtr &pkt, int & lat, assert(offset < blkSize); assert(pkt->getSize() <= blkSize); assert(offset + pkt->getSize() <=blkSize); - memcpy(pkt->getPtr(), blk->data + offset, + std::memcpy(pkt->getPtr(), blk->data + offset, pkt->getSize()); } return blk; @@ -176,7 +177,7 @@ Cache::handleAccess(PacketPtr &pkt, int & lat, if (blk->checkWrite(pkt->req)) { write_data = true; blk->status |= BlkDirty; - memcpy(blk->data + offset, pkt->getPtr(), + std::memcpy(blk->data + offset, pkt->getPtr(), pkt->getSize()); } } else { @@ -184,7 +185,7 @@ Cache::handleAccess(PacketPtr &pkt, int & lat, if (pkt->req->isLocked()) { blk->trackLoadLocked(pkt->req); } - memcpy(pkt->getPtr(), blk->data + offset, + std::memcpy(pkt->getPtr(), blk->data + offset, pkt->getSize()); } @@ -228,7 +229,7 @@ Cache::handleFill(BlkType *blk, PacketPtr &pkt, if (pkt->isRead()) { - memcpy(blk->data, pkt->getPtr(), blkSize); + std::memcpy(blk->data, pkt->getPtr(), blkSize); } blk->whenReady = pkt->finishTime; @@ -249,14 +250,14 @@ Cache::handleFill(BlkType *blk, PacketPtr &pkt, if (target->isWrite()) { if (blk->checkWrite(pkt->req)) { blk->status |= BlkDirty; - memcpy(blk->data + target->getOffset(blkSize), + std::memcpy(blk->data + target->getOffset(blkSize), target->getPtr(), target->getSize()); } } else { if (pkt->req->isLocked()) { blk->trackLoadLocked(pkt->req); } - memcpy(target->getPtr(), + std::memcpy(target->getPtr(), blk->data + target->getOffset(blkSize), target->getSize()); } @@ -285,7 +286,7 @@ Cache::handleFill(BlkType *blk, MSHR * mshr, blk = doReplacement(blk, pkt, new_state, writebacks); if (pkt->isRead()) { - memcpy(blk->data, pkt->getPtr(), blkSize); + std::memcpy(blk->data, pkt->getPtr(), blkSize); } blk->whenReady = pkt->finishTime; @@ -337,14 +338,14 @@ Cache::handleFill(BlkType *blk, MSHR * mshr, if (target->isWrite()) { if (blk->checkWrite(pkt->req)) { blk->status |= BlkDirty; - memcpy(blk->data + target->getOffset(blkSize), + std::memcpy(blk->data + target->getOffset(blkSize), target->getPtr(), target->getSize()); } } else { if (pkt->req->isLocked()) { blk->trackLoadLocked(pkt->req); } - memcpy(target->getPtr(), + std::memcpy(target->getPtr(), blk->data + target->getOffset(blkSize), target->getSize()); } @@ -384,7 +385,7 @@ Cache::handleSnoop(BlkType *blk, assert(offset < blkSize); assert(pkt->getSize() <= blkSize); assert(offset + pkt->getSize() <=blkSize); - memcpy(pkt->getPtr(), blk->data + offset, pkt->getSize()); + std::memcpy(pkt->getPtr(), blk->data + offset, pkt->getSize()); handleSnoop(blk, new_state); } @@ -431,7 +432,7 @@ Cache::writebackBlk(BlkType *blk) new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0); PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1); writeback->allocate(); - memcpy(writeback->getPtr(),blk->data,blkSize); + std::memcpy(writeback->getPtr(),blk->data,blkSize); blk->status &= ~BlkDirty; return writeback; @@ -463,7 +464,7 @@ Cache::verifyData(BlkType *blk) assert(blkSize == blk->size); } - retval = memcmp(tmp_data, blk->data, blkSize) == 0; + retval = std::memcmp(tmp_data, blk->data, blkSize) == 0; delete [] tmp_data; return retval; } @@ -664,7 +665,7 @@ Cache::sendResult(PacketPtr &pkt, MSHR* mshr, DPRINTF(Cache, "Block for blk addr %x moving from state " "%i to %i\n", pkt->getAddr(), old_state, new_state); //Set the state on the upgrade - memcpy(pkt->getPtr(), blk->data, blkSize); + std::memcpy(pkt->getPtr(), blk->data, blkSize); PacketList writebacks; handleFill(blk, mshr, new_state, writebacks, pkt); assert(writebacks.empty()); @@ -839,7 +840,7 @@ Cache::snoop(PacketPtr &pkt) assert(offset < blkSize); assert(pkt->getSize() <= blkSize); assert(offset + pkt->getSize() <=blkSize); - memcpy(pkt->getPtr(), mshr->pkt->getPtr() + offset, pkt->getSize()); + std::memcpy(pkt->getPtr(), mshr->pkt->getPtr() + offset, pkt->getSize()); respondToSnoop(pkt, curTick + hitLatency); } diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 4a431d82d..a1af88341 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -32,6 +32,7 @@ * @file * Definitions of a simple buffer for a blocking cache. */ +#include #include "mem/cache/base_cache.hh" #include "mem/cache/miss/blocking_buffer.hh" @@ -60,7 +61,7 @@ BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time) wb.allocate(pkt->cmd, blk_addr, blk_size, pkt); } - memcpy(wb.pkt->getPtr(), pkt->getPtr(), blk_size); + std::memcpy(wb.pkt->getPtr(), pkt->getPtr(), blk_size); cache->setBlocked(Blocked_NoWBBuffers); cache->setMasterRequest(Request_WB, time); @@ -147,7 +148,7 @@ BlockingBuffer::handleResponse(PacketPtr &pkt, Tick time) PacketPtr target = ((MSHR*)(pkt->senderState))->getTarget(); ((MSHR*)(pkt->senderState))->popTarget(); if (pkt->isRead()) { - memcpy(target->getPtr(), pkt->getPtr(), target->getSize()); + std::memcpy(target->getPtr(), pkt->getPtr(), target->getSize()); } cache->respond(target, time); assert(!((MSHR*)(pkt->senderState))->hasTargets()); @@ -191,7 +192,7 @@ BlockingBuffer::doWriteback(Addr addr, PacketPtr pkt = new Packet(req, Packet::Writeback, -1); pkt->allocate(); if (data) { - memcpy(pkt->getPtr(), data, size); + std::memcpy(pkt->getPtr(), data, size); } if (compressed) { @@ -217,7 +218,7 @@ BlockingBuffer::doWriteback(PacketPtr &pkt) // Since allocate as buffer copies the request, // need to copy data here. - memcpy(wb.pkt->getPtr(), pkt->getPtr(), pkt->getSize()); + std::memcpy(wb.pkt->getPtr(), pkt->getPtr(), pkt->getSize()); cache->setBlocked(Blocked_NoWBBuffers); cache->setMasterRequest(Request_WB, curTick); diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index 205068a8c..24386a249 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -90,6 +90,7 @@ public: PacketPtr &target) { fatal("Unimplemented"); + M5_DUMMY_RETURN } /** @@ -201,6 +202,7 @@ public: MSHR* allocateTargetList(Addr addr) { fatal("Unimplemented"); + M5_DUMMY_RETURN } }; diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 38f9662ea..e547e112e 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -527,7 +527,7 @@ IIC::hash(Addr addr) const { tag = extractTag(addr); mask = hashSets-1; /* assumes iic_hash_size is a power of 2 */ x = tag & mask; - y = (tag >> (int)(::log(hashSets)/::log(2))) & mask; + y = (tag >> (int)(::log((double)hashSets)/::log((double)2))) & mask; assert (x < hashSets && y < hashSets); return x ^ y; #endif diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 4b94adca6..75272544c 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -36,6 +36,7 @@ #ifndef __LRU_HH__ #define __LRU_HH__ +#include #include #include "mem/cache/cache_blk.hh" // base class @@ -273,7 +274,7 @@ public: */ void readData(LRUBlk *blk, uint8_t *data) { - memcpy(data, blk->data, blk->size); + std::memcpy(data, blk->data, blk->size); } /** diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh index e6ace0921..840b68940 100644 --- a/src/mem/cache/tags/split.hh +++ b/src/mem/cache/tags/split.hh @@ -36,6 +36,7 @@ #ifndef __SPLIT_HH__ #define __SPLIT_HH__ +#include #include #include "mem/cache/cache_blk.hh" // base class @@ -234,6 +235,7 @@ class Split : public BaseTags int extractSet(Addr addr) const { panic("should never call this!\n"); + M5_DUMMY_RETURN } /** @@ -281,7 +283,7 @@ class Split : public BaseTags */ void readData(SplitBlk *blk, uint8_t *data) { - memcpy(data, blk->data, blk->size); + std::memcpy(data, blk->data, blk->size); } /** diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh index 9001cdb14..0f8adf18d 100644 --- a/src/mem/cache/tags/split_lifo.hh +++ b/src/mem/cache/tags/split_lifo.hh @@ -36,6 +36,7 @@ #ifndef __SPLIT_LIFO_HH__ #define __SPLIT_LIFO_HH__ +#include #include #include "mem/cache/cache_blk.hh" // base class @@ -296,7 +297,7 @@ public: */ void readData(SplitBlk *blk, uint8_t *data) { - memcpy(data, blk->data, blk->size); + std::memcpy(data, blk->data, blk->size); } /** diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh index e17a478d3..eb65445ea 100644 --- a/src/mem/cache/tags/split_lru.hh +++ b/src/mem/cache/tags/split_lru.hh @@ -36,6 +36,7 @@ #ifndef __SPLIT_LRU_HH__ #define __SPLIT_LRU_HH__ +#include #include #include "mem/cache/cache_blk.hh" // base class @@ -279,7 +280,7 @@ public: */ void readData(SplitBlk *blk, uint8_t *data) { - memcpy(data, blk->data, blk->size); + std::memcpy(data, blk->data, blk->size); } /** diff --git a/src/mem/dram.cc b/src/mem/dram.cc index 873ca5b97..394c70db6 100644 --- a/src/mem/dram.cc +++ b/src/mem/dram.cc @@ -102,7 +102,7 @@ Kluwer Academic, pages 291-310, March, 2000. #include "mem/dram.hh" #include "sim/builder.hh" - +#include #include extern int maxThreadsPerCPU; @@ -203,7 +203,7 @@ DRAMMemory::DRAMMemory(Params *p) last_bank = num_banks+1; last_row = num_rows; busy_until = new Tick[num_banks]; - memset(busy_until,0,sizeof(Tick)*num_banks); /* initiliaze */ + std::memset(busy_until,0,sizeof(Tick)*num_banks); /* initiliaze */ } diff --git a/src/mem/packet.cc b/src/mem/packet.cc index e2faf4527..44805236c 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -36,7 +36,7 @@ */ #include - +#include #include "base/misc.hh" #include "base/trace.hh" #include "mem/packet.hh" @@ -183,7 +183,7 @@ fixPacket(PacketPtr func, PacketPtr timing) if (func->isRead()) { if (funcStart >= timingStart && funcEnd <= timingEnd) { func->allocate(); - memcpy(func->getPtr(), timing->getPtr() + + std::memcpy(func->getPtr(), timing->getPtr() + funcStart - timingStart, func->getSize()); func->result = Packet::Success; func->flags |= SATISFIED; @@ -199,11 +199,11 @@ fixPacket(PacketPtr func, PacketPtr timing) } } else if (func->isWrite()) { if (funcStart >= timingStart) { - memcpy(timing->getPtr() + (funcStart - timingStart), + std::memcpy(timing->getPtr() + (funcStart - timingStart), func->getPtr(), (std::min(funcEnd, timingEnd) - funcStart) + 1); } else { // timingStart > funcStart - memcpy(timing->getPtr(), + std::memcpy(timing->getPtr(), func->getPtr() + (timingStart - funcStart), (std::min(funcEnd, timingEnd) - timingStart) + 1); } diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 7d616a4e5..eccd42bec 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -59,7 +59,7 @@ PhysicalMemory::PhysicalMemory(Params *p) int map_flags = MAP_ANON | MAP_PRIVATE; pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, - map_flags, -1, 0); + map_flags, -1, 0); if (pmemAddr == (void *)MAP_FAILED) { perror("mmap"); @@ -84,7 +84,7 @@ PhysicalMemory::init() PhysicalMemory::~PhysicalMemory() { if (pmemAddr) - munmap(pmemAddr, params()->addrRange.size()); + munmap((char*)pmemAddr, params()->addrRange.size()); //Remove memPorts? } @@ -430,7 +430,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) // unmap file that was mmaped in the constructor // This is done here to make sure that gzip and open don't muck with our // nice large space of memory before we reallocate it - munmap(pmemAddr, params()->addrRange.size()); + munmap((char*)pmemAddr, params()->addrRange.size()); pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0); diff --git a/src/mem/port.cc b/src/mem/port.cc index bbc98c160..da719bbd9 100644 --- a/src/mem/port.cc +++ b/src/mem/port.cc @@ -32,6 +32,7 @@ * @file * Port object definitions. */ +#include #include "base/chunk_generator.hh" #include "base/trace.hh" @@ -78,7 +79,7 @@ Port::memsetBlob(Addr addr, uint8_t val, int size) // quick and dirty... uint8_t *buf = new uint8_t[size]; - memset(buf, val, size); + std::memset(buf, val, size); blobHelper(addr, buf, size, Packet::WriteReq); delete [] buf; diff --git a/src/mem/port.hh b/src/mem/port.hh index 75afc04e6..5e55225bf 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -159,7 +159,7 @@ class Port this function to be called, a DMA interface doesn't really have a block size, so it is defaulted to a panic. */ - virtual int deviceBlockSize() { panic("??"); } + virtual int deviceBlockSize() { panic("??"); M5_DUMMY_RETURN } /** The peer port is requesting us to reply with a list of the ranges we are responsible for. @@ -261,8 +261,10 @@ class FunctionalPort : public Port {} protected: - virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir"); } - virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir"); } + virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir"); + M5_DUMMY_RETURN } + virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir"); + M5_DUMMY_RETURN } virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); } virtual void recvStatusChange(Status status) {} diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh index 7b1ae701e..f8e5215cf 100644 --- a/src/sim/byteswap.hh +++ b/src/sim/byteswap.hh @@ -47,7 +47,7 @@ // If one doesn't exist, we pretty much get what is listed below, so it all // works out #include -#elif defined (__sun__) +#elif defined (__sun) #include #else #include -- cgit v1.2.3 From 2939d7d061efc8444c06ac52f82c8aeaf0048aaf Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:57:16 -0500 Subject: Make Sparc traceflag even more chatty some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232 --- src/arch/sparc/floatregfile.cc | 6 ++++ src/arch/sparc/isa/base.isa | 26 +++++++++++++++- src/arch/sparc/isa/decoder.isa | 25 ++++++++------- src/arch/sparc/isa/formats/basic.isa | 3 +- src/arch/sparc/isa/formats/mem/util.isa | 6 +++- src/cpu/exetrace.cc | 54 ++++++++++++++++++--------------- src/cpu/m5legion_interface.h | 5 +-- 7 files changed, 82 insertions(+), 43 deletions(-) (limited to 'src') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 7f3d5a758..1bb78c67b 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -72,16 +72,19 @@ FloatReg FloatRegFile::readReg(int floatReg, int width) float32_t result32; memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); result = htog(result32); + DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result); break; case DoubleWidth: float64_t result64; memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); result = htog(result64); + DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result); break; case QuadWidth: float128_t result128; memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); result = htog(result128); + DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result); break; default: panic("Attempted to read a %d bit floating point register!", width); @@ -101,16 +104,19 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) uint32_t result32; memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); result = htog(result32); + DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result); break; case DoubleWidth: uint64_t result64; memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); result = htog(result64); + DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result); break; case QuadWidth: uint64_t result128; memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); result = htog(result128); + DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result); break; default: panic("Attempted to read a %d bit floating point register!", width); diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index 4a806bfd0..5b65ec288 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -290,3 +290,27 @@ output decoder {{ } }}; +output exec {{ + /// Check "FP enabled" machine status bit. Called when executing any FP + /// instruction in full-system mode. + /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled + /// if not. Non-full-system mode: always returns NoFault. +#if FULL_SYSTEM + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + Fault fault = NoFault; // dummy... this ipr access should not fault + if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef && + xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4) + return NoFault; + else + return new FpDisabled; + } +#else + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + return NoFault; + } +#endif +}}; + + diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 425ebc9d0..852fddfcf 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -186,7 +186,7 @@ decode OP default Unknown::unknown() Y = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); + Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); @@ -246,8 +246,7 @@ decode OP default Unknown::unknown() Rd = resTemp = Rs1 + val2 + carryin;}}, {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, - {{(Rs1<63:1> + val2<63:1> + - ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, + {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} ); 0x1A: umulcc({{ @@ -257,16 +256,16 @@ decode OP default Unknown::unknown() {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ int64_t resTemp; - Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); + Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = Ccr<0:0>; Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, - {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} ); 0x1D: udivxcc({{ @@ -664,7 +663,7 @@ decode OP default Unknown::unknown() Fsr &= ~(7 << 14); Fsr &= ~(0x1F); }}); - 0x03: Trap::fmovq({{fault = new FpDisabled;}}); + 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); 0x05: fnegs({{ Frds.uw = Frs2s.uw ^ (1UL << 31); //fsr.ftt = fsr.cexc = 0 @@ -860,11 +859,11 @@ decode OP default Unknown::unknown() 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); - 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); + 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}}); 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); - 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); + 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}}); 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 0x7C: Trap::for({{fault = new IllegalInstruction;}}); @@ -1130,14 +1129,14 @@ decode OP default Unknown::unknown() {{ Mem.uw = Rd.uw; Rd.uw = uReg0;}}, {{EXT_ASI}}); format Trap { - 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); + 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 0x21: decode X { 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); } 0x22: ldqf({{fault = new FpDisabled;}}); 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); - 0x24: Store::stf({{Mem.uw = Frd.uw;}}); + 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 0x25: decode X { 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); @@ -1145,7 +1144,7 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); + 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { @@ -1228,7 +1227,7 @@ decode OP default Unknown::unknown() {{fault = new DataAccessException;}}); } } - 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); + 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 0x36: stqfa({{fault = new FpDisabled;}}); format StoreAlt { 0x37: decode EXT_ASI { diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a4c05387b..db6efd229 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -71,6 +71,7 @@ def template BasicExecute {{ { Fault fault = NoFault; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(code)s; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index b6e0945b7..3b02f58de 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -141,6 +141,7 @@ def template LoadExecute {{ { Fault fault = NoFault; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -169,6 +170,7 @@ def template LoadExecute {{ Fault fault = NoFault; Addr EA; uint%(mem_acc_size)s_t Mem; + %(fp_enable_check)s; %(ea_decl)s; %(ea_rd)s; %(ea_code)s; @@ -206,6 +208,7 @@ def template StoreExecute {{ //It should be optomized out in all the others bool storeCond = true; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -235,6 +238,7 @@ def template StoreExecute {{ Fault fault = NoFault; bool storeCond = true; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 26e8b6b44..9ea90681c 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -293,7 +293,8 @@ Trace::InstRecord::dump(ostream &outs) bool diffPC = false; bool diffCC = false; bool diffInst = false; - bool diffRegs = false; + bool diffIntRegs = false; + bool diffFpRegs = false; bool diffTpc = false; bool diffTnpc = false; bool diffTstate = false; @@ -357,10 +358,15 @@ Trace::InstRecord::dump(ostream &outs) } for (int i = 0; i < TheISA::NumIntArchRegs; i++) { if (thread->readIntReg(i) != shared_data->intregs[i]) { - diffRegs = true; + diffIntRegs = true; } } - uint64_t oldTl = thread->readMiscReg(MISCREG_TL); + for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { + if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { + diffFpRegs = true; + } + } + uint64_t oldTl = thread->readMiscReg(MISCREG_TL); if (oldTl != shared_data->tl) diffTl = true; for (int i = 1; i <= MaxTL; i++) { @@ -426,12 +432,12 @@ Trace::InstRecord::dump(ostream &outs) diffTlb = true; } - if ((diffPC || diffCC || diffInst || diffRegs || diffTpc || - diffTnpc || diffTstate || diffTt || diffHpstate || - diffHtstate || diffHtba || diffPstate || diffY || - diffCcr || diffTl || diffGl || diffAsi || diffPil || - diffCwp || diffCansave || diffCanrestore || - diffOtherwin || diffCleanwin || diffTlb) + if ((diffPC || diffCC || diffInst || diffIntRegs || + diffFpRegs || diffTpc || diffTnpc || diffTstate || + diffTt || diffHpstate || diffHtstate || diffHtba || + diffPstate || diffY || diffCcr || diffTl || diffGl || + diffAsi || diffPil || diffCwp || diffCansave || + diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) @@ -444,8 +450,10 @@ Trace::InstRecord::dump(ostream &outs) outs << " [CC]"; if (diffInst) outs << " [Instruction]"; - if (diffRegs) + if (diffIntRegs) outs << " [IntRegs]"; + if (diffFpRegs) + outs << " [FpRegs]"; if (diffTpc) outs << " [Tpc]"; if (diffTnpc) @@ -588,26 +596,22 @@ Trace::InstRecord::dump(ostream &outs) printSectionHeader(outs, "General Purpose Registers"); static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; - for(int y = 0; y < 4; y++) - { - for(int x = 0; x < 8; x++) - { + for(int y = 0; y < 4; y++) { + for(int x = 0; x < 8; x++) { char label[8]; sprintf(label, "%s%d", regtypes[y], x); printRegPair(outs, label, thread->readIntReg(y*8+x), shared_data->intregs[y*8+x]); - /*outs << regtypes[y] << x << " " ; - outs << "0x" << hex << setw(16) - << thread->readIntReg(y*8+x); - if (thread->readIntReg(y*8 + x) - != shared_data->intregs[y*8+x]) - outs << " X "; - else - outs << " | "; - outs << "0x" << setw(16) << hex - << shared_data->intregs[y*8+x] - << endl;*/ + } + } + if (diffFpRegs) { + for (int x = 0; x < 32; x++) { + char label[8]; + sprintf(label, "%%f%d", x); + printRegPair(outs, label, + thread->readFloatRegBits(x,FloatRegFile::DoubleWidth), + shared_data->fpregs[x]); } } if (diffTlb) { diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index c3ba5986e..81714f769 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2006-2007 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,7 @@ #include -#define VERSION 0xA1000007 +#define VERSION 0xA1000008 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -47,6 +47,7 @@ typedef struct { uint32_t instruction; uint32_t new_instruction; uint64_t intregs[32]; + uint64_t fpregs[32]; uint64_t tpc[8]; uint64_t tnpc[8]; -- cgit v1.2.3 From de9ac2153ec110143ed2c575d8ac60022836ad58 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 19:00:17 -0500 Subject: forgot to include this file --HG-- extra : convert_revision : 4b570a33a951e9286b38873b2be3651ffaee8532 --- src/base/compiler.hh | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 src/base/compiler.hh (limited to 'src') diff --git a/src/base/compiler.hh b/src/base/compiler.hh new file mode 100644 index 000000000..5f2e9d7af --- /dev/null +++ b/src/base/compiler.hh @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __BASE_COMPILER_HH__ +#define __BASE_COMPILER_HH__ + +//http://msdn2.microsoft.com/en-us/library/ms937669.aspx +//http://msdn2.microsoft.com/en-us/library/aa448724.aspx +//http://docs.sun.com/source/819-3688/sun.specific.html#marker-998278 +//http://gcc.gnu.org/onlinedocs/gcc-3.3.1/gcc/Function-Attributes.html#Function%20Attributes + +#if defined(__GNUC__) +#define M5_ATTR_NORETURN __attribute__((noreturn)) +#define M5_PRAGMA_NORETURN(x) +#define M5_DUMMY_RETURN +#elif defined(__SUNPRO_CC) +// this doesn't do anything with sun cc, but why not +#define M5_ATTR_NORETURN __sun_attr__((__noreturn__)) +#define M5_DUMMY_RETURN return (0); +#define M5_PRAGMA_NORETURN(x) _Pragma("does_not_return(x)") +#else +#error "Need to define compiler options in base/compiler.hh" +#endif + +#endif // __BASE_COMPILER_HH__ -- cgit v1.2.3