From daebe18e897b3dc87f2e8b156ce03691c8b930c7 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 12 Jan 2010 10:17:19 -0800 Subject: faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way. --- src/sim/faults.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/sim/faults.cc b/src/sim/faults.cc index 0fe853785..6149a8335 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -40,7 +40,7 @@ #if !FULL_SYSTEM void FaultBase::invoke(ThreadContext * tc) { - fatal("fault (%s) detected @ PC %p", name(), tc->readPC()); + panic("fault (%s) detected @ PC %p", name(), tc->readPC()); } #else void FaultBase::invoke(ThreadContext * tc) @@ -54,7 +54,7 @@ void FaultBase::invoke(ThreadContext * tc) void UnimpFault::invoke(ThreadContext * tc) { - fatal("Unimpfault: %s\n", panicStr.c_str()); + panic("Unimpfault: %s\n", panicStr.c_str()); } #if !FULL_SYSTEM -- cgit v1.2.3 From 9f635484784a9a523fc356df9e55922660d13d8f Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 12 Jan 2010 10:22:46 -0800 Subject: since totalInstructions() is impl'ed by all the cpus, make it an abstract base class. --- src/cpu/base.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index bfeec0870..b229ddd38 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -274,7 +274,7 @@ class BaseCPU : public MemObject */ virtual BranchPred *getBranchPred() { return NULL; }; - virtual Counter totalInstructions() const { return 0; } + virtual Counter totalInstructions() const = 0; // Function tracing private: -- cgit v1.2.3 From 8b4e8690b73f61ae0bb2cb052ec56f58d1d531e2 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Tue, 12 Jan 2010 10:53:02 -0800 Subject: cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations. --- src/mem/cache/cache_impl.hh | 9 ++++++--- src/mem/cache/tags/fa_lru.cc | 4 ++-- src/mem/cache/tags/fa_lru.hh | 4 ++-- src/mem/cache/tags/iic.cc | 4 ++-- src/mem/cache/tags/iic.hh | 4 ++-- src/mem/cache/tags/lru.cc | 4 ++-- src/mem/cache/tags/lru.hh | 4 ++-- 7 files changed, 18 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 429928c79..2397a17c5 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -266,7 +266,8 @@ Cache::access(PacketPtr pkt, BlkType *&blk, return false; } - blk = tags->accessBlock(pkt->getAddr(), lat); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + blk = tags->accessBlock(pkt->getAddr(), lat, id); DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), pkt->req->isInstFetch() ? " (ifetch)" : "", @@ -299,7 +300,8 @@ Cache::access(PacketPtr pkt, BlkType *&blk, incMissCount(pkt); return false; } - tags->insertBlock(pkt->getAddr(), blk); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + tags->insertBlock(pkt->getAddr(), blk, id); blk->status = BlkValid | BlkReadable; } std::memcpy(blk->data, pkt->getPtr(), blkSize); @@ -976,7 +978,8 @@ Cache::handleFill(PacketPtr pkt, BlkType *blk, tempBlock->tag = tags->extractTag(addr); DPRINTF(Cache, "using temp block for %x\n", addr); } else { - tags->insertBlock(addr, blk); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + tags->insertBlock(pkt->getAddr(), blk, id); } } else { // existing block... probably an upgrade diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 122e6e14b..808f9e25a 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -154,7 +154,7 @@ FALRU::invalidateBlk(FALRU::BlkType *blk) } FALRUBlk* -FALRU::accessBlock(Addr addr, int &lat, int *inCache) +FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache) { accesses++; int tmp_in_cache = 0; @@ -228,7 +228,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks) } void -FALRU::insertBlock(Addr addr, FALRU::BlkType *blk) +FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src) { } diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 4e6bccc1d..b20d25d2b 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -182,7 +182,7 @@ public: * @param inCache The FALRUBlk::inCache flags. * @return Pointer to the cache block. */ - FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0); + FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0); /** * Find the block in the cache, do not update the replacement data. @@ -200,7 +200,7 @@ public: */ FALRUBlk* findVictim(Addr addr, PacketList & writebacks); - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Return the hit latency of this cache. diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index b9ba5256b..a8ef4e6fb 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -219,7 +219,7 @@ IIC::regStats(const string &name) IICTag* -IIC::accessBlock(Addr addr, int &lat) +IIC::accessBlock(Addr addr, int &lat, int context_src) { Addr tag = extractTag(addr); unsigned set = hash(addr); @@ -338,7 +338,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks) } void -IIC::insertBlock(Addr addr, BlkType* blk) +IIC::insertBlock(Addr addr, BlkType* blk, int context_src) { } diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 994f7b8f7..c96cdaf3e 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -422,7 +422,7 @@ class IIC : public BaseTags * @param lat The access latency. * @return A pointer to the block found, if any. */ - IICTag* accessBlock(Addr addr, int &lat); + IICTag* accessBlock(Addr addr, int &lat, int context_src); /** * Find the block, do not update the replacement data. @@ -440,7 +440,7 @@ class IIC : public BaseTags */ IICTag* findVictim(Addr addr, PacketList &writebacks); - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Called at end of simulation to complete average block reference stats. diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 9371f193a..81d82c231 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -150,7 +150,7 @@ LRU::~LRU() } LRUBlk* -LRU::accessBlock(Addr addr, int &lat) +LRU::accessBlock(Addr addr, int &lat, int context_src) { Addr tag = extractTag(addr); unsigned set = extractSet(addr); @@ -200,7 +200,7 @@ LRU::findVictim(Addr addr, PacketList &writebacks) } void -LRU::insertBlock(Addr addr, LRU::BlkType *blk) +LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src) { if (!blk->isTouched) { tagsInUse++; diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 2874d8f1f..ecd6e861f 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -172,7 +172,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - LRUBlk* accessBlock(Addr addr, int &lat); + LRUBlk* accessBlock(Addr addr, int &lat, int context_src); /** * Finds the given address in the cache, do not update replacement data. @@ -197,7 +197,7 @@ public: * @param addr The address to update. * @param blk The block to update. */ - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Generate the tag from the given address. -- cgit v1.2.3 From 4a40ac71f8679ea7c15efb45afd522bf4d3b3e73 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 18 Jan 2010 14:30:31 -0800 Subject: util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator. --- src/mem/page_table.cc | 12 +++++++++++- src/sim/serialize.cc | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 4bc3a4434..88cfdfeb7 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -222,6 +222,16 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); pTable[vaddr] = *entry; ++i; - } + } + + process->M5_pid = pTable[vaddr].asn; + +#if THE_ISA == ALPHA_ISA + // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work + // correctly + int id = process->contextIds[0]; + ThreadContext *tc = process->system->getThreadContext(id); + tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57); +#endif } diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index 5ae9128e5..1663d18bc 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -422,7 +422,7 @@ Serializable::serializeAll(const string &cpt_dir) time_t t = time(NULL); if (!outstream.is_open()) fatal("Unable to open file %s for writing\n", cpt_file.c_str()); - outstream << "// checkpoint generated: " << ctime(&t); + outstream << "## checkpoint generated: " << ctime(&t); globals.serialize(outstream); SimObject::serializeAll(outstream); -- cgit v1.2.3