From 0a26883296597a8737a0fbf2ce4cc625d85f842c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 1 Feb 2012 09:48:28 -0800 Subject: configs: More fixes for the memory system updates --- src/dev/arm/RealView.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index dc2219cd1..3da47399e 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -351,10 +351,11 @@ class VExpress_ELT(RealView): def attachOnChipIO(self, bus, bridge): self.gic.pio = bus.port self.a9scu.pio = bus.port + self.local_cpu_timer.pio = bus.port # Bridge ranges based on excluding what is part of on-chip I/O # (gic, a9scu) bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), - AddrRange(self.local_cpu_timer.pio_addr, Addr.max)] + AddrRange(self.l2x0_fake.pio_addr, Addr.max)] # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the @@ -363,7 +364,6 @@ class VExpress_ELT(RealView): self.elba_uart.pio = bus.port self.uart.pio = bus.port self.realview_io.pio = bus.port - self.local_cpu_timer.pio = bus.port self.v2m_timer0.pio = bus.port self.v2m_timer1.pio = bus.port self.elba_timer0.pio = bus.port -- cgit v1.2.3