From 0bd751848096d7446075e4c8aec43b1798deda67 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 26 Dec 2006 01:43:18 -0500
Subject: Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.

--HG--
extra : convert_revision : 5c334ec806305451b3883c7fd0ed9cd695c038bc
---
 src/cpu/o3/commit_impl.hh | 7 +++----
 src/cpu/o3/iew_impl.hh    | 2 --
 src/cpu/o3/lsq_unit.hh    | 2 --
 3 files changed, 3 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index d8236f077..c3c4983c5 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -988,20 +988,19 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
                     "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
                     head_inst->seqNum, head_inst->readPC());
 
-#if !FULL_SYSTEM
             // Hack to make sure syscalls/memory barriers/quiesces
             // aren't executed until all stores write back their data.
             // This direct communication shouldn't be used for
             // anything other than this.
-            if (inst_num > 0 || iewStage->hasStoresToWB())
-#else
             if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
                     head_inst->isQuiesce()) &&
                 iewStage->hasStoresToWB())
-#endif
             {
                 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
                 return false;
+            } else if (inst_num > 0) {
+                DPRINTF(Commit, "Waiting to become head of commit.\n");
+                return false;
             }
 
             toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index d239bd951..a8962f2f7 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1124,13 +1124,11 @@ DefaultIEW<Impl>::dispatchInsts(unsigned tid)
             }
 
             toRename->iewInfo[tid].dispatchedToLSQ++;
-#if FULL_SYSTEM
         } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
             // Same as non-speculative stores.
             inst->setCanCommit();
             instQueue.insertBarrier(inst);
             add_to_iq = false;
-#endif
         } else if (inst->isNonSpeculative()) {
             DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
                     "encountered, skipping.\n", tid);
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a2e11173e..14f9d5031 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -509,7 +509,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             "storeHead: %i addr: %#x\n",
             load_idx, store_idx, storeHead, req->getPaddr());
 
-#if FULL_SYSTEM
     if (req->isLocked()) {
         // Disable recording the result temporarily.  Writing to misc
         // regs normally updates the result, but this is not the
@@ -518,7 +517,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
         TheISA::handleLockedRead(load_inst.get(), req);
         load_inst->recordResult = true;
     }
-#endif
 
     while (store_idx != -1) {
         // End once we've reached the top of the LSQ
-- 
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