From 9a6e896d3bc904745f090aad1a6d40f04f5ac2ef Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 10 Nov 2006 22:41:21 -0500 Subject: Big fix for functional access, where we forgot to copy the last byte on write intersections. src/mem/packet.cc: Make sure to copy the whole data (we were one byte short) src/mem/tport.cc: Fix for the proper semantics of fixPacket --HG-- extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8 --- src/mem/packet.cc | 5 +++-- src/mem/tport.cc | 6 +++--- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mem/packet.cc b/src/mem/packet.cc index a342af634..938116ab5 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -168,6 +168,7 @@ fixPacket(PacketPtr func, PacketPtr timing) memcpy(func->getPtr(), timing->getPtr() + funcStart - timingStart, func->getSize()); func->result = Packet::Success; + func->flags |= SATISFIED; return false; } else { // In this case the timing packet only partially satisfies the @@ -182,11 +183,11 @@ fixPacket(PacketPtr func, PacketPtr timing) if (funcStart >= timingStart) { memcpy(timing->getPtr() + (funcStart - timingStart), func->getPtr(), - std::min(funcEnd, timingEnd) - funcStart); + (std::min(funcEnd, timingEnd) - funcStart) + 1); } else { // timingStart > funcStart memcpy(timing->getPtr(), func->getPtr() + (timingStart - funcStart), - std::min(funcEnd, timingEnd) - timingStart); + (std::min(funcEnd, timingEnd) - timingStart) + 1); } // we always want to keep going with a write return true; diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 086d91279..a85ae2b14 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -35,14 +35,14 @@ SimpleTimingPort::recvFunctional(PacketPtr pkt) { std::list >::iterator i = transmitList.begin(); std::list >::iterator end = transmitList.end(); - bool done = false; + bool notDone = true; - while (i != end && !done) { + while (i != end && notDone) { PacketPtr target = i->second; // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) - done = fixPacket(pkt, target); + notDone = fixPacket(pkt, target); i++; } -- cgit v1.2.3 From f876bc2bf0e04b888c2748c0cabf8d11b31f41b7 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 10 Nov 2006 22:45:50 -0500 Subject: More fixes for functional accesses. It now makes the writeback memory leak to crash all configs. Working on that now. src/mem/cache/base_cache.cc: Keep a list of the responders so we can search them on functional accesses. src/mem/cache/base_cache.hh: Properly put things on a list for responses so we can search the list. Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there) src/mem/cache/cache_impl.hh: Properly return when the first read hit on a functional access. Make sure to call to check the other ports list of packets before forwarding it out. --HG-- extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a --- src/mem/cache/base_cache.cc | 87 ++++++++++++++++++++++--------- src/mem/cache/base_cache.hh | 121 ++++++++++++++++++++++++++++++++++++++++---- src/mem/cache/cache_impl.hh | 21 ++++---- 3 files changed, 187 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index c26d7782b..489a24d4c 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -102,21 +102,51 @@ BaseCache::CachePort::recvAtomic(PacketPtr pkt) return cache->doAtomicAccess(pkt, isCpuSide); } -void -BaseCache::CachePort::recvFunctional(PacketPtr pkt) +bool +BaseCache::CachePort::checkFunctional(PacketPtr pkt) { //Check storage here first list::iterator i = drainList.begin(); - list::iterator end = drainList.end(); - for (; i != end; ++i) { + list::iterator iend = drainList.end(); + bool notDone = true; + while (i != iend && notDone) { PacketPtr target = *i; // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { - fixPacket(pkt, target); + notDone = fixPacket(pkt, target); } + i++; + } + //Also check the response not yet ready to be on the list + std::list >::iterator j = transmitList.begin(); + std::list >::iterator jend = transmitList.end(); + + while (j != jend && notDone) { + PacketPtr target = j->second; + // If the target contains data, and it overlaps the + // probed request, need to update data + if (target->intersect(pkt)) + notDone = fixPacket(pkt, target); + j++; } - cache->doFunctionalAccess(pkt, isCpuSide); + return notDone; +} + +void +BaseCache::CachePort::recvFunctional(PacketPtr pkt) +{ + bool notDone = checkFunctional(pkt); + if (notDone) + cache->doFunctionalAccess(pkt, isCpuSide); +} + +void +BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt) +{ + bool notDone = checkFunctional(pkt); + if (notDone) + sendFunctional(pkt); } void @@ -135,7 +165,7 @@ BaseCache::CachePort::recvRetry() isCpuSide && cache->doSlaveRequest()) { DPRINTF(CachePort, "%s has more responses/requests\n", name()); - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); reqCpu->schedule(curTick + 1); } waitingOnRetry = false; @@ -176,7 +206,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); reqCpu->schedule(curTick + 1); } } @@ -194,7 +224,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); reqCpu->schedule(curTick + 1); } } @@ -226,23 +256,19 @@ BaseCache::CachePort::clearBlocked() } } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort) - : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) +BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), + newResponse(_newResponse) { - this->setFlags(AutoDelete); + if (!newResponse) + this->setFlags(AutoDelete); pkt = NULL; } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt) - : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt) -{ - this->setFlags(AutoDelete); -} - void BaseCache::CacheEvent::process() { - if (!pkt) + if (!newResponse) { if (cachePort->waitingOnRetry) return; //We have some responses to drain first @@ -322,8 +348,16 @@ BaseCache::CacheEvent::process() } return; } - //Response - //Know the packet to send + //Else it's a response Response + assert(cachePort->transmitList.size()); + assert(cachePort->transmitList.front().first <= curTick); + pkt = cachePort->transmitList.front().second; + cachePort->transmitList.pop_front(); + if (!cachePort->transmitList.empty()) { + Tick time = cachePort->transmitList.front().first; + schedule(time <= curTick ? curTick+1 : time); + } + if (pkt->flags & NACKED_LINE) pkt->result = Packet::Nacked; else @@ -343,7 +377,7 @@ BaseCache::CacheEvent::process() } // Check if we're done draining once this list is empty - if (cachePort->drainList.empty()) + if (cachePort->drainList.empty() && cachePort->transmitList.empty()) cachePort->cache->checkDrain(); } @@ -358,8 +392,10 @@ BaseCache::getPort(const std::string &if_name, int idx) { if (if_name == "") { - if(cpuSidePort == NULL) + if(cpuSidePort == NULL) { cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true); + sendEvent = new CacheEvent(cpuSidePort, true); + } return cpuSidePort; } else if (if_name == "functional") @@ -368,8 +404,10 @@ BaseCache::getPort(const std::string &if_name, int idx) } else if (if_name == "cpu_side") { - if(cpuSidePort == NULL) + if(cpuSidePort == NULL) { cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true); + sendEvent = new CacheEvent(cpuSidePort, true); + } return cpuSidePort; } else if (if_name == "mem_side") @@ -377,6 +415,7 @@ BaseCache::getPort(const std::string &if_name, int idx) if (memSidePort != NULL) panic("Already have a mem side for this cache\n"); memSidePort = new CachePort(name() + "-mem_side_port", this, false); + memSendEvent = new CacheEvent(memSidePort, true); return memSidePort; } else panic("Port name %s unrecognized\n", if_name); diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index ea7544fbb..9a79bd36c 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -105,7 +105,11 @@ class BaseCache : public MemObject void clearBlocked(); - bool canDrain() { return drainList.empty(); } + bool checkFunctional(PacketPtr pkt); + + void checkAndSendFunctional(PacketPtr pkt); + + bool canDrain() { return drainList.empty() && transmitList.empty(); } bool blocked; @@ -117,15 +121,16 @@ class BaseCache : public MemObject std::list drainList; + std::list > transmitList; }; struct CacheEvent : public Event { CachePort *cachePort; PacketPtr pkt; + bool newResponse; - CacheEvent(CachePort *_cachePort); - CacheEvent(CachePort *_cachePort, PacketPtr _pkt); + CacheEvent(CachePort *_cachePort, bool response); void process(); const char *description(); }; @@ -133,6 +138,9 @@ class BaseCache : public MemObject public: //Made public so coherence can get at it. CachePort *cpuSidePort; + CacheEvent *sendEvent; + CacheEvent *memSendEvent; + protected: CachePort *memSidePort; @@ -353,6 +361,12 @@ class BaseCache : public MemObject snoopRangesSent = false; } + ~BaseCache() + { + delete sendEvent; + delete memSendEvent; + } + virtual void init(); /** @@ -467,7 +481,8 @@ class BaseCache : public MemObject { if (!doMasterRequest() && !memSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort); + BaseCache::CacheEvent * reqCpu = + new BaseCache::CacheEvent(memSidePort, false); reqCpu->schedule(time); } uint8_t flag = 1<waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort); + BaseCache::CacheEvent * reqCpu = + new BaseCache::CacheEvent(cpuSidePort, false); reqCpu->schedule(time); } uint8_t flag = 1<= curTick); if (pkt->needsResponse()) { - CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); +/* CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); reqCpu->schedule(time); +*/ + if (cpuSidePort->transmitList.empty()) { + assert(!sendEvent->scheduled()); + sendEvent->schedule(time); + cpuSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + + // something is on the list and this belongs at the end + if (time >= cpuSidePort->transmitList.back().first) { + cpuSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + // Something is on the list and this belongs somewhere else + std::list >::iterator i = + cpuSidePort->transmitList.begin(); + std::list >::iterator end = + cpuSidePort->transmitList.end(); + bool done = false; + + while (i != end && !done) { + if (time < i->first) + cpuSidePort->transmitList.insert(i,std::pair + (time,pkt)); + i++; + } } else { if (pkt->cmd != Packet::UpgradeReq) @@ -548,12 +593,42 @@ class BaseCache : public MemObject */ void respondToMiss(PacketPtr pkt, Tick time) { + assert(time >= curTick); if (!pkt->req->isUncacheable()) { - missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time; + missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += + time - pkt->time; } if (pkt->needsResponse()) { - CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); +/* CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); reqCpu->schedule(time); +*/ + if (cpuSidePort->transmitList.empty()) { + assert(!sendEvent->scheduled()); + sendEvent->schedule(time); + cpuSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + + // something is on the list and this belongs at the end + if (time >= cpuSidePort->transmitList.back().first) { + cpuSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + // Something is on the list and this belongs somewhere else + std::list >::iterator i = + cpuSidePort->transmitList.begin(); + std::list >::iterator end = + cpuSidePort->transmitList.end(); + bool done = false; + + while (i != end && !done) { + if (time < i->first) + cpuSidePort->transmitList.insert(i,std::pair + (time,pkt)); + i++; + } } else { if (pkt->cmd != Packet::UpgradeReq) @@ -570,9 +645,37 @@ class BaseCache : public MemObject */ void respondToSnoop(PacketPtr pkt, Tick time) { + assert(time >= curTick); assert (pkt->needsResponse()); - CacheEvent *reqMem = new CacheEvent(memSidePort, pkt); +/* CacheEvent *reqMem = new CacheEvent(memSidePort, pkt); reqMem->schedule(time); +*/ + if (memSidePort->transmitList.empty()) { + assert(!memSendEvent->scheduled()); + memSendEvent->schedule(time); + memSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + + // something is on the list and this belongs at the end + if (time >= memSidePort->transmitList.back().first) { + memSidePort->transmitList.push_back(std::pair + (time,pkt)); + return; + } + // Something is on the list and this belongs somewhere else + std::list >::iterator i = + memSidePort->transmitList.begin(); + std::list >::iterator end = + memSidePort->transmitList.end(); + bool done = false; + + while (i != end && !done) { + if (time < i->first) + memSidePort->transmitList.insert(i,std::pair(time,pkt)); + i++; + } } /** diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 9bb72e85c..176d9159a 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -536,7 +536,7 @@ Cache::probe(PacketPtr &pkt, bool update, if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) { // Still need to change data in all locations. - otherSidePort->sendFunctional(pkt); + otherSidePort->checkAndSendFunctional(pkt); if (pkt->isRead() && pkt->result == Packet::Success) return 0; } @@ -560,30 +560,33 @@ Cache::probe(PacketPtr &pkt, bool update, missQueue->findWrites(blk_addr, writes); if (!update) { + bool notDone = !(pkt->flags & SATISFIED); //Hit in cache (was a block) // Check for data in MSHR and writebuffer. if (mshr) { MSHR::TargetList *targets = mshr->getTargetList(); MSHR::TargetList::iterator i = targets->begin(); MSHR::TargetList::iterator end = targets->end(); - for (; i != end; ++i) { + for (; i != end && notDone; ++i) { PacketPtr target = *i; // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { - fixPacket(pkt, target); + DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a MSHR\n", + blk_addr); + notDone = fixPacket(pkt, target); } } } - for (int i = 0; i < writes.size(); ++i) { + for (int i = 0; i < writes.size() && notDone; ++i) { PacketPtr write = writes[i]->pkt; if (write->intersect(pkt)) { - fixPacket(pkt, write); + DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a writeback\n", + pkt->cmdString(), blk_addr); + notDone = fixPacket(pkt, write); } } - if (pkt->isRead() - && pkt->result != Packet::Success - && otherSidePort == memSidePort) { - otherSidePort->sendFunctional(pkt); + if (notDone && otherSidePort == memSidePort) { + otherSidePort->checkAndSendFunctional(pkt); assert(pkt->result == Packet::Success); } return 0; -- cgit v1.2.3 From b16e5591773c362f10808ab439b27a87d891f0fc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 11 Nov 2006 17:22:10 -0800 Subject: Get rid of the ParamContext for pseudo instructions and move the parameters to the BaseCPU object. --HG-- extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e --- src/cpu/base.hh | 4 ++++ src/cpu/o3/alpha/cpu_builder.cc | 12 ++++++++++ src/cpu/ozone/cpu_builder.cc | 10 +++++++++ src/cpu/simple/atomic.cc | 10 +++++++++ src/cpu/simple/timing.cc | 10 +++++++++ src/python/m5/objects/BaseCPU.py | 6 +++++ src/sim/pseudo_inst.cc | 48 +++++++--------------------------------- 7 files changed, 60 insertions(+), 40 deletions(-) (limited to 'src') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 9257778ef..788f77e3a 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -155,6 +155,10 @@ class BaseCPU : public MemObject int cpu_id; #if FULL_SYSTEM Tick profile; + + bool do_statistics_insts; + bool do_checkpoint_insts; + bool do_quiesce; #endif Tick progress_interval; BaseCPU *checker; diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index be8ad8de6..09ccc7f65 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -57,6 +57,10 @@ Param cpu_id; SimObjectParam itb; SimObjectParam dtb; Param profile; + +Param do_quiesce; +Param do_checkpoint_insts; +Param do_statistics_insts; #else SimObjectVectorParam workload; #endif // FULL_SYSTEM @@ -163,6 +167,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), INIT_PARAM(profile, ""), + + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "Processes to run"), #endif // FULL_SYSTEM @@ -306,6 +314,10 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->workload = workload; #endif // FULL_SYSTEM diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 39337dbff..155f0ce09 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -64,6 +64,10 @@ Param cpu_id; SimObjectParam itb; SimObjectParam dtb; Param profile; + +Param do_quiesce; +Param do_checkpoint_insts; +Param do_statistics_insts #else SimObjectVectorParam workload; //SimObjectParam page_table; @@ -184,6 +188,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "Processes to run"), // INIT_PARAM(page_table, "Page table"), @@ -341,6 +348,9 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->workload = workload; // params->pTable = page_table; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..e9679cc7c 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -500,6 +500,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) SimObjectParam itb; SimObjectParam dtb; Param profile; + + Param do_quiesce; + Param do_checkpoint_insts; + Param do_statistics_insts; #else SimObjectParam workload; #endif // FULL_SYSTEM @@ -532,6 +536,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM @@ -569,6 +576,9 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->process = workload; #endif diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index abf316095..db2c940c0 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -665,6 +665,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) SimObjectParam itb; SimObjectParam dtb; Param profile; + + Param do_quiesce; + Param do_checkpoint_insts; + Param do_statistics_insts; #else SimObjectParam workload; #endif // FULL_SYSTEM @@ -697,6 +701,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) INIT_PARAM(itb, "Instruction TLB"), INIT_PARAM(dtb, "Data TLB"), INIT_PARAM(profile, ""), + INIT_PARAM(do_quiesce, ""), + INIT_PARAM(do_checkpoint_insts, ""), + INIT_PARAM(do_statistics_insts, ""), #else INIT_PARAM(workload, "processes to run"), #endif // FULL_SYSTEM @@ -732,6 +739,9 @@ CREATE_SIM_OBJECT(TimingSimpleCPU) params->itb = itb; params->dtb = dtb; params->profile = profile; + params->do_quiesce = do_quiesce; + params->do_checkpoint_insts = do_checkpoint_insts; + params->do_statistics_insts = do_statistics_insts; #else params->process = workload; #endif diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6e05627d..36474a6a4 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -15,6 +15,12 @@ class BaseCPU(SimObject): cpu_id = Param.Int("CPU identifier") if build_env['FULL_SYSTEM']: + do_qiesce = Param.Bool(True, "enable quiesce instructions") + do_checkpoint_insts = Param.Bool(True, + "enable checkpoint pseudo instructions") + do_statistics_insts = Param.Bool(True, + "enable statistics pseudo instructions") + if build_env['TARGET_ISA'] == 'sparc': dtb = Param.SparcDTB(SparcDTB(), "Data TLB") itb = Param.SparcITB(SparcITB(), "Instruction TLB") diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 66036def1..4a8c0eb66 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -40,7 +40,6 @@ #include "cpu/thread_context.hh" #include "cpu/quiesce_event.hh" #include "arch/kernel_stats.hh" -#include "sim/param.hh" #include "sim/pseudo_inst.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" @@ -57,10 +56,6 @@ using namespace TheISA; namespace AlphaPseudo { - bool doStatisticsInsts; - bool doCheckpointInsts; - bool doQuiesce; - void arm(ThreadContext *tc) { @@ -71,7 +66,7 @@ namespace AlphaPseudo void quiesce(ThreadContext *tc) { - if (!doQuiesce) + if (!tc->getCpuPtr()->params->do_quiesce) return; DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name()); @@ -84,7 +79,7 @@ namespace AlphaPseudo void quiesceNs(ThreadContext *tc, uint64_t ns) { - if (!doQuiesce || ns == 0) + if (!tc->getCpuPtr()->params->do_quiesce || ns == 0) return; EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); @@ -107,7 +102,7 @@ namespace AlphaPseudo void quiesceCycles(ThreadContext *tc, uint64_t cycles) { - if (!doQuiesce || cycles == 0) + if (!tc->getCpuPtr()->params->do_quiesce || cycles == 0) return; EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); @@ -197,7 +192,7 @@ namespace AlphaPseudo void resetstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -211,7 +206,7 @@ namespace AlphaPseudo void dumpstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -252,7 +247,7 @@ namespace AlphaPseudo void dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { - if (!doStatisticsInsts) + if (!tc->getCpuPtr()->params->do_statistics_insts) return; @@ -266,7 +261,7 @@ namespace AlphaPseudo void m5checkpoint(ThreadContext *tc, Tick delay, Tick period) { - if (!doCheckpointInsts) + if (!tc->getCpuPtr()->params->do_checkpoint_insts) return; Tick when = curTick + delay * Clock::Int::ns; @@ -278,7 +273,7 @@ namespace AlphaPseudo uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) { - const string &file = tc->getCpuPtr()->system->params()->readfile; + const string &file = tc->getSystemPtr()->params()->readfile; if (file.empty()) { return ULL(0); } @@ -310,33 +305,6 @@ namespace AlphaPseudo return result; } - class Context : public ParamContext - { - public: - Context(const string §ion) : ParamContext(section) {} - void checkParams(); - }; - - Context context("pseudo_inst"); - - Param __quiesce(&context, "quiesce", - "enable quiesce instructions", - true); - Param __statistics(&context, "statistics", - "enable statistics pseudo instructions", - true); - Param __checkpoint(&context, "checkpoint", - "enable checkpoint pseudo instructions", - true); - - void - Context::checkParams() - { - doQuiesce = __quiesce; - doStatisticsInsts = __statistics; - doCheckpointInsts = __checkpoint; - } - void debugbreak(ThreadContext *tc) { debug_break(); -- cgit v1.2.3 From 3f280bb2e86ed8282862ec8fae84b8061f290bf7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 11 Nov 2006 20:46:56 -0800 Subject: set TRACING_ON one way or another explicitly in the SConscript file instead of basing it on DEBUG --HG-- extra : convert_revision : 6e6807cc4350ef92baeaaabfeb3dc0bb785128ba --- src/SConscript | 7 ++++--- src/base/trace.hh | 8 -------- 2 files changed, 4 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/SConscript b/src/SConscript index 44bcb5320..929ed8278 100644 --- a/src/SConscript +++ b/src/SConscript @@ -316,16 +316,17 @@ else: makeEnv('debug', '.do', CCFLAGS = Split('%s -O0' % debug_flag), - CPPDEFINES = 'DEBUG') + CPPDEFINES = ['DEBUG', 'TRACING_ON=1']) # Optimized binary makeEnv('opt', '.o', - CCFLAGS = Split('-g -O3')) + CCFLAGS = Split('-g -O3'), + CPPDEFINES = ['TRACING_ON=1']) # "Fast" binary makeEnv('fast', '.fo', strip = True, CCFLAGS = Split('-O3'), - CPPDEFINES = 'NDEBUG') + CPPDEFINES = ['NDEBUG', 'TRACING_ON=0']) # Profiled binary makeEnv('prof', '.po', diff --git a/src/base/trace.hh b/src/base/trace.hh index 8df5dd893..9b053990c 100644 --- a/src/base/trace.hh +++ b/src/base/trace.hh @@ -39,14 +39,6 @@ #include "sim/host.hh" #include "sim/root.hh" -#ifndef TRACING_ON -#ifndef NDEBUG -#define TRACING_ON 1 -#else -#define TRACING_ON 0 -#endif -#endif - #include "base/traceflags.hh" namespace Trace { -- cgit v1.2.3 From 8354cfc7151f4623aedee1e4b32157aa4c038707 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 11 Nov 2006 23:57:20 -0800 Subject: Fix Typo --HG-- extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8 --- src/python/m5/objects/BaseCPU.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 36474a6a4..2f702a4bf 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -15,7 +15,7 @@ class BaseCPU(SimObject): cpu_id = Param.Int("CPU identifier") if build_env['FULL_SYSTEM']: - do_qiesce = Param.Bool(True, "enable quiesce instructions") + do_quiesce = Param.Bool(True, "enable quiesce instructions") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, -- cgit v1.2.3 From c577665040342bf27808bfdea272626e4dac786d Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 06:35:39 -0500 Subject: Fix functional access errors related to delayed respnoses in cachePort src/mem/cache/base_cache.cc: On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag. src/mem/packet.cc: src/mem/packet.hh: Create a wrapper to toggle the hasData flag on delayed responses --HG-- extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901 --- src/mem/cache/base_cache.cc | 11 ++++++++--- src/mem/packet.cc | 18 ++++++++++++++++++ src/mem/packet.hh | 14 +++++++++++++- 3 files changed, 39 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 489a24d4c..c16cb6945 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -114,6 +114,8 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt) // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { + DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a drain\n", + pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1)); notDone = fixPacket(pkt, target); } i++; @@ -126,8 +128,11 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt) PacketPtr target = j->second; // If the target contains data, and it overlaps the // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); + if (target->intersect(pkt)) { + DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a response\n", + pkt->cmdString(), pkt->getAddr() & ~(cache->getBlockSize() - 1)); + notDone = fixDelayedResponsePacket(pkt, target); + } j++; } return notDone; @@ -348,7 +353,7 @@ BaseCache::CacheEvent::process() } return; } - //Else it's a response Response + //Else it's a response assert(cachePort->transmitList.size()); assert(cachePort->transmitList.front().first <= curTick); pkt = cachePort->transmitList.front().second; diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 938116ab5..e2faf4527 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -143,6 +143,24 @@ Packet::intersect(PacketPtr p) return !(s1 > e2 || e1 < s2); } +bool +fixDelayedResponsePacket(PacketPtr func, PacketPtr timing) +{ + bool result; + + if (timing->isRead() || timing->isWrite()) { + timing->toggleData(); + result = fixPacket(func, timing); + timing->toggleData(); + } + else { + //Don't toggle if it isn't a read/write response + result = fixPacket(func, timing); + } + + return result; +} + bool fixPacket(PacketPtr func, PacketPtr timing) { diff --git a/src/mem/packet.hh b/src/mem/packet.hh index cb97dd036..2bc51bf12 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -344,6 +344,13 @@ class Packet srcValid = false; } + + void toggleData() { + int icmd = (int)cmd; + icmd ^= HasData; + cmd = (Command)icmd; + } + /** * Take a request packet and modify it in place to be suitable for * returning as a response to that request. @@ -448,7 +455,6 @@ class Packet bool intersect(PacketPtr p); }; - /** This function given a functional packet and a timing packet either satisfies * the timing packet, or updates the timing packet to reflect the updated state * in the timing packet. It returns if the functional packet should continue to @@ -456,6 +462,12 @@ class Packet */ bool fixPacket(PacketPtr func, PacketPtr timing); +/** This function is a wrapper for the fixPacket field that toggles the hasData bit + * it is used when a response is waiting in the caches, but hasn't been marked as a + * response yet (so the fixPacket needs to get the correct value for the hasData) + */ +bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing); + std::ostream & operator<<(std::ostream &o, const Packet &p); #endif //__MEM_PACKET_HH -- cgit v1.2.3 From b22d390721275fec8c07bd57d9ed021e78f3f3f7 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 06:36:33 -0500 Subject: Yet another small bug in mem system related to flow control src/mem/cache/cache_impl.hh: When upgrades change to readEx make sure to allocate the block Fix dprintf --HG-- extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded --- src/mem/cache/cache_impl.hh | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 176d9159a..51aa4f8e7 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -333,6 +333,8 @@ Cache::handleResponse(PacketPtr &pkt) DPRINTF(Cache, "Handling reponse to %x\n", pkt->getAddr()); if (pkt->isCacheFill() && !pkt->isNoAllocate()) { + DPRINTF(Cache, "Block for addr %x being updated in Cache\n", + pkt->getAddr()); blk = tags->findBlock(pkt); CacheBlk::State old_state = (blk) ? blk->status : 0; PacketList writebacks; @@ -483,9 +485,15 @@ Cache::snoop(PacketPtr &pkt) respondToSnoop(pkt, curTick + hitLatency); return; } - if (blk) + if (blk) { DPRINTF(Cache, "Cache snooped a %s request for addr %x, " "new state is %i\n", pkt->cmdString(), blk_addr, new_state); + if (mshr && !mshr->inService && new_state == 0) { + //There was a outstanding write to a shared block, not need ReadEx + //not update, so change No Allocate param in MSHR + mshr->pkt->flags &= ~NO_ALLOCATE; + } + } tags->handleSnoop(blk, new_state); } @@ -534,7 +542,7 @@ Cache::probe(PacketPtr &pkt, bool update, } } - if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) { + if (!update && (otherSidePort == cpuSidePort)) { // Still need to change data in all locations. otherSidePort->checkAndSendFunctional(pkt); if (pkt->isRead() && pkt->result == Packet::Success) @@ -572,7 +580,7 @@ Cache::probe(PacketPtr &pkt, bool update, // probed request, need to update data if (target->intersect(pkt)) { DPRINTF(Cache, "Functional %s access to blk_addr %x intersects a MSHR\n", - blk_addr); + pkt->cmdString(), blk_addr); notDone = fixPacket(pkt, target); } } -- cgit v1.2.3 From 11accacf7c9de8147e68845051a489c251c4e7b1 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 06:44:05 -0500 Subject: Move code before a early return to make sure it is executed on all paths --HG-- extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85 --- src/mem/cache/cache_impl.hh | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 51aa4f8e7..8acc67b69 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -476,6 +476,13 @@ Cache::snoop(PacketPtr &pkt) } CacheBlk::State new_state; bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); + + if (blk && mshr && !mshr->inService && new_state == 0) { + //There was a outstanding write to a shared block, not need ReadEx + //not update, so change No Allocate param in MSHR + mshr->pkt->flags &= ~NO_ALLOCATE; + } + if (satisfy) { DPRINTF(Cache, "Cache snooped a %s request for addr %x and " "now supplying data, new state is %i\n", @@ -485,15 +492,10 @@ Cache::snoop(PacketPtr &pkt) respondToSnoop(pkt, curTick + hitLatency); return; } - if (blk) { + if (blk) DPRINTF(Cache, "Cache snooped a %s request for addr %x, " "new state is %i\n", pkt->cmdString(), blk_addr, new_state); - if (mshr && !mshr->inService && new_state == 0) { - //There was a outstanding write to a shared block, not need ReadEx - //not update, so change No Allocate param in MSHR - mshr->pkt->flags &= ~NO_ALLOCATE; - } - } + tags->handleSnoop(blk, new_state); } -- cgit v1.2.3 From 29cefcbf1353b90f6b12334f8554efa87bd659c8 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 07:16:34 -0500 Subject: Don't insert reponses into the list more than once If you get inserted in the front, reschedule the event --HG-- extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965 --- src/mem/cache/base_cache.hh | 26 ++++++++++++++++++++++---- src/mem/tport.cc | 8 +++++++- 2 files changed, 29 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 9a79bd36c..584c2d5df 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -571,9 +571,15 @@ class BaseCache : public MemObject bool done = false; while (i != end && !done) { - if (time < i->first) + if (time < i->first) { + if (i == cpuSidePort->transmitList.begin()) { + //Inserting at begining, reschedule + sendEvent->reschedule(time); + } cpuSidePort->transmitList.insert(i,std::pair (time,pkt)); + done = true; + } i++; } } @@ -624,9 +630,15 @@ class BaseCache : public MemObject bool done = false; while (i != end && !done) { - if (time < i->first) + if (time < i->first) { + if (i == cpuSidePort->transmitList.begin()) { + //Inserting at begining, reschedule + sendEvent->reschedule(time); + } cpuSidePort->transmitList.insert(i,std::pair (time,pkt)); + done = true; + } i++; } } @@ -672,8 +684,14 @@ class BaseCache : public MemObject bool done = false; while (i != end && !done) { - if (time < i->first) - memSidePort->transmitList.insert(i,std::pair(time,pkt)); + if (time < i->first) { + if (i == memSidePort->transmitList.begin()) { + //Inserting at begining, reschedule + memSendEvent->reschedule(time); + } + memSidePort->transmitList.insert(i,std::pair(time,pkt)); + done = true; + } i++; } } diff --git a/src/mem/tport.cc b/src/mem/tport.cc index a85ae2b14..c43c9aac0 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -118,8 +118,14 @@ SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) bool done = false; while (i != end && !done) { - if (time+curTick < i->first) + if (time+curTick < i->first) { + if (i == transmitList.begin()) { + //Inserting at begining, reschedule + sendEvent.reschedule(time+curTick); + } transmitList.insert(i,std::pair(time+curTick,pkt)); + done = true; + } i++; } } -- cgit v1.2.3 From a200bccc2065d776d0face971610588f438998e7 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 09:06:15 -0500 Subject: Handle packets being deleted by lower level properly. Fixes for Mem Leak associated with Writebacks. src/mem/cache/miss/mshr_queue.cc: Fixes for Mem Leak associated with Writebacks. (Double Delete removed) --HG-- extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416 --- src/mem/cache/cache_impl.hh | 25 +++++++++++++++++-------- src/mem/cache/miss/mshr_queue.cc | 5 ----- 2 files changed, 17 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 8acc67b69..df59b0a4f 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -53,6 +53,8 @@ #include "sim/sim_exit.hh" // for SimExitEvent +bool SIGNAL_NACK_HACK; + template bool Cache:: @@ -242,6 +244,11 @@ Cache::access(PacketPtr &pkt) missQueue->handleMiss(pkt, size, curTick + hitLatency); } + if (pkt->cmd == Packet::Writeback) { + //Need to clean up the packet on a writeback miss, but leave the request + delete pkt; + } + return true; } @@ -265,6 +272,7 @@ Cache::getPacket() assert(!doMasterRequest() || missQueue->havePending()); assert(!pkt || pkt->time <= curTick); + SIGNAL_NACK_HACK = false; return pkt; } @@ -273,16 +281,15 @@ void Cache::sendResult(PacketPtr &pkt, MSHR* mshr, bool success) { - if (success && !(pkt && (pkt->flags & NACKED_LINE))) { - if (!mshr->pkt->needsResponse() - && !(mshr->pkt->cmd == Packet::UpgradeReq) - && (pkt && (pkt->flags & SATISFIED))) { - //Writeback, clean up the non copy version of the packet - delete pkt; - } + if (success && !(SIGNAL_NACK_HACK)) { + //Remember if it was an upgrade because writeback MSHR's are removed + //in Mark in Service + bool upgrade = (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq); + missQueue->markInService(mshr->pkt, mshr); + //Temp Hack for UPGRADES - if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) { + if (upgrade) { assert(pkt); //Upgrades need to be fixed pkt->flags &= ~CACHE_LINE_FILL; BlkType *blk = tags->findBlock(pkt); @@ -300,6 +307,7 @@ Cache::sendResult(PacketPtr &pkt, MSHR* mshr, } } else if (pkt && !pkt->req->isUncacheable()) { pkt->flags &= ~NACKED_LINE; + SIGNAL_NACK_HACK = false; pkt->flags &= ~SATISFIED; pkt->flags &= ~SNOOP_COMMIT; @@ -404,6 +412,7 @@ Cache::snoop(PacketPtr &pkt) assert(!(pkt->flags & SATISFIED)); pkt->flags |= SATISFIED; pkt->flags |= NACKED_LINE; + SIGNAL_NACK_HACK = true; ///@todo NACK's from other levels //warn("NACKs from devices not connected to the same bus " //"not implemented\n"); diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index d3a7a7933..6cb62429d 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -198,11 +198,6 @@ MSHRQueue::markInService(MSHR* mshr) //assert(mshr == pendingList.front()); if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) { assert(mshr->getNumTargets() == 0); - if ((mshr->pkt->flags & SATISFIED) && (mshr->pkt->cmd == Packet::Writeback)) { - //Writeback hit, so delete it - //otherwise the consumer will delete it - delete mshr->pkt->req; - } deallocate(mshr); return; } -- cgit v1.2.3 From 5edfaefc78c72540a17f65973118eec873019f17 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Sun, 12 Nov 2006 09:30:12 -0500 Subject: Physical memory overrides the tport version of recvFunctional, need to do the check here for responses that match as well --HG-- extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f --- src/mem/physical.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src') diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 39eb63108..94f60ad80 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -288,6 +288,21 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) void PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) { + //Since we are overriding the function, make sure to have the impl of the + //check or functional accesses here. + std::list >::iterator i = transmitList.begin(); + std::list >::iterator end = transmitList.end(); + bool notDone = true; + + while (i != end && notDone) { + PacketPtr target = i->second; + // If the target contains data, and it overlaps the + // probed request, need to update data + if (target->intersect(pkt)) + notDone = fixPacket(pkt, target); + i++; + } + // Default implementation of SimpleTimingPort::recvFunctional() // calls recvAtomic() and throws away the latency; we can save a // little here by just not calculating the latency. -- cgit v1.2.3 From d2d44317528ffadf81fbb95c92291d8d2d4a2190 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sun, 12 Nov 2006 18:49:16 -0800 Subject: Create a module called internal where swigged stuff goes. Rename cc_main to internal.main --HG-- extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072 --- src/SConscript | 3 ++- src/python/SConscript | 6 +++--- src/python/m5/SimObject.py | 9 ++++----- src/python/m5/__init__.py | 28 ++++++++++++++-------------- src/python/m5/main.py | 6 +++--- src/python/m5/params.py | 7 ++++--- src/sim/main.cc | 8 +++++--- 7 files changed, 35 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/SConscript b/src/SConscript index 929ed8278..385047f7f 100644 --- a/src/SConscript +++ b/src/SConscript @@ -129,12 +129,13 @@ base_sources = Split(''' mem/cache/cache_builder.cc + python/swig/main_wrap.cc + sim/builder.cc sim/debug.cc sim/eventq.cc sim/faults.cc sim/main.cc - python/swig/cc_main_wrap.cc sim/param.cc sim/root.cc sim/serialize.cc diff --git a/src/python/SConscript b/src/python/SConscript index c9e713199..5c351c32a 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -98,12 +98,12 @@ pyzip_files.append('m5/defines.py') pyzip_files.append('m5/info.py') pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) -env.Command(['swig/cc_main_wrap.cc', 'm5/cc_main.py'], - 'swig/cc_main.i', +env.Command(['swig/main_wrap.cc', 'm5/internal/main.py'], + 'swig/main.i', '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES') -pyzip_dep_files.append('m5/cc_main.py') +pyzip_dep_files.append('m5/internal/main.py') # Action function to build the zip archive. Uses the PyZipFile module # included in the standard Python library. diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 18b3fff55..934358298 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -695,7 +695,7 @@ class SimObject(object): def getCCObject(self): if not self._ccObject: self._ccObject = -1 # flag to catch cycles in recursion - self._ccObject = cc_main.createSimObject(self.path()) + self._ccObject = internal.main.createSimObject(self.path()) elif self._ccObject == -1: raise RuntimeError, "%s: recursive call to getCCObject()" \ % self.path() @@ -730,13 +730,13 @@ class SimObject(object): # i don't know if there's a better way to do this - calling # setMemoryMode directly from self._ccObject results in calling # SimObject::setMemoryMode, not the System::setMemoryMode - system_ptr = cc_main.convertToSystemPtr(self._ccObject) + system_ptr = internal.main.convertToSystemPtr(self._ccObject) system_ptr.setMemoryMode(mode) for child in self._children.itervalues(): child.changeTiming(mode) def takeOverFrom(self, old_cpu): - cpu_ptr = cc_main.convertToBaseCPUPtr(old_cpu._ccObject) + cpu_ptr = internal.main.convertToBaseCPUPtr(old_cpu._ccObject) self._ccObject.takeOverFrom(cpu_ptr) # generate output file for 'dot' to display as a pretty graph. @@ -795,8 +795,7 @@ def resolveSimObject(name): # short to avoid polluting other namespaces. __all__ = ['SimObject', 'ParamContext'] - # see comment on imports at end of __init__.py. import proxy -import cc_main +import internal import m5 diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 579562b38..f39cc670a 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -30,11 +30,11 @@ import atexit, os, sys # import the SWIG-wrapped main C++ functions -import cc_main +import internal # import a few SWIG-wrapped items (those that are likely to be used # directly by user scripts) completely into this module for # convenience -from cc_main import simulate, SimLoopExitEvent +from internal.main import simulate, SimLoopExitEvent # import the m5 compile options import defines @@ -85,10 +85,10 @@ def instantiate(root): root.print_ini() sys.stdout.close() # close config.ini sys.stdout = sys.__stdout__ # restore to original - cc_main.loadIniFile(resolveSimObject) # load config.ini into C++ + internal.main.loadIniFile(resolveSimObject) # load config.ini into C++ root.createCCObject() root.connectPorts() - cc_main.finalInit() + internal.main.finalInit() noDot = True # temporary until we fix dot if not noDot: dot = pydot.Dot() @@ -102,10 +102,10 @@ def instantiate(root): # Export curTick to user script. def curTick(): - return cc_main.cvar.curTick + return internal.main.cvar.curTick # register our C++ exit callback function with Python -atexit.register(cc_main.doExitCleanup) +atexit.register(internal.main.doExitCleanup) # This loops until all objects have been fully drained. def doDrain(root): @@ -119,7 +119,7 @@ def doDrain(root): # be drained. def drain(root): all_drained = False - drain_event = cc_main.createCountedDrain() + drain_event = internal.main.createCountedDrain() unready_objects = root.startDrain(drain_event, True) # If we've got some objects that can't drain immediately, then simulate if unready_objects > 0: @@ -127,7 +127,7 @@ def drain(root): simulate() else: all_drained = True - cc_main.cleanupCountedDrain(drain_event) + internal.main.cleanupCountedDrain(drain_event) return all_drained def resume(root): @@ -138,12 +138,12 @@ def checkpoint(root, dir): raise TypeError, "Object is not a root object. Checkpoint must be called on a root object." doDrain(root) print "Writing checkpoint" - cc_main.serializeAll(dir) + internal.main.serializeAll(dir) resume(root) def restoreCheckpoint(root, dir): print "Restoring from checkpoint" - cc_main.unserializeAll(dir) + internal.main.unserializeAll(dir) resume(root) def changeToAtomic(system): @@ -152,7 +152,7 @@ def changeToAtomic(system): "called on a root object." doDrain(system) print "Changing memory mode to atomic" - system.changeTiming(cc_main.SimObject.Atomic) + system.changeTiming(internal.main.SimObject.Atomic) def changeToTiming(system): if not isinstance(system, objects.Root) and not isinstance(system, objects.System): @@ -160,7 +160,7 @@ def changeToTiming(system): "called on a root object." doDrain(system) print "Changing memory mode to timing" - system.changeTiming(cc_main.SimObject.Timing) + system.changeTiming(internal.main.SimObject.Timing) def switchCpus(cpuList): print "switching cpus" @@ -180,7 +180,7 @@ def switchCpus(cpuList): raise TypeError, "%s is not of type BaseCPU" % cpu # Drain all of the individual CPUs - drain_event = cc_main.createCountedDrain() + drain_event = internal.main.createCountedDrain() unready_cpus = 0 for old_cpu in old_cpus: unready_cpus += old_cpu.startDrain(drain_event, False) @@ -188,7 +188,7 @@ def switchCpus(cpuList): if unready_cpus > 0: drain_event.setCount(unready_cpus) simulate() - cc_main.cleanupCountedDrain(drain_event) + internal.main.cleanupCountedDrain(drain_event) # Now all of the CPUs are ready to be switched out for old_cpu in old_cpus: old_cpu._ccObject.switchOut() diff --git a/src/python/m5/main.py b/src/python/m5/main.py index ef37f62ac..1e224c0cf 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -211,7 +211,7 @@ def parse_args(): return opts,args def main(): - import cc_main + import internal parse_args() @@ -249,7 +249,7 @@ def main(): print "M5 Simulator System" print brief_copyright print - print "M5 compiled %s" % cc_main.cvar.compileDate; + print "M5 compiled %s" % internal.main.cvar.compileDate; print "M5 started %s" % datetime.now().ctime() print "M5 executing on %s" % socket.gethostname() print "command line:", @@ -264,7 +264,7 @@ def main(): usage(2) # tell C++ about output directory - cc_main.setOutputDir(options.outdir) + internal.main.setOutputDir(options.outdir) # update the system path with elements from the -p option sys.path[0:0] = options.path diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 4b5953bcb..9e5f985c3 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -830,8 +830,9 @@ class PortRef(object): if self.ccConnected: # already done this return peer = self.peer - cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index, - peer.simobj.getCCObject(), peer.name, peer.index) + internal.main.connectPorts(self.simobj.getCCObject(), self.name, + self.index, peer.simobj.getCCObject(), + peer.name, peer.index) self.ccConnected = True peer.ccConnected = True @@ -970,4 +971,4 @@ __all__ = ['Param', 'VectorParam', from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass import proxy import objects -import cc_main +import internal diff --git a/src/sim/main.cc b/src/sim/main.cc index 5b44102a8..6037283a4 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -117,7 +117,9 @@ abortHandler(int sigtype) #endif } -extern "C" { void init_cc_main(); } +extern "C" { +void init_main(); +} int main(int argc, char **argv) @@ -155,8 +157,8 @@ main(int argc, char **argv) Py_Initialize(); PySys_SetArgv(argc, argv); - // initialize SWIG 'cc_main' module - init_cc_main(); + // initialize SWIG 'm5.internal.main' module + init_main(); PyRun_SimpleString("import m5.main"); PyRun_SimpleString("m5.main.main()"); -- cgit v1.2.3