From 30bc897613a1ee36ed887eb9da1579bd9828186e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 3 Sep 2008 00:52:54 -0400 Subject: X86: Fix the microcode for sign/zero extending moves that use high byte registers. --- src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index d9a83dfde..35f0436f5 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -126,7 +126,8 @@ def macroop MOVSXD_R_P { }; def macroop MOVSX_B_R_R { - sexti reg, regm, 7 + mov t1, t1, regm, dataSize=1 + sexti reg, t1, 7 }; def macroop MOVSX_B_R_M { @@ -160,7 +161,8 @@ def macroop MOVSX_W_R_P { # def macroop MOVZX_B_R_R { - zexti reg, regm, 7 + mov t1, t1, regm, dataSize=1 + zexti reg, t1, 7 }; def macroop MOVZX_B_R_M { -- cgit v1.2.3