From 3e1ad73d089a455a559bed6779996877b7370b50 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Wed, 23 Feb 2011 16:35:04 -0500 Subject: inorder: dyn inst initialization remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function --- src/cpu/inorder/inorder_dyn_inst.cc | 67 ++++++++++++++++--------------------- src/cpu/inorder/inorder_dyn_inst.hh | 48 +++++++------------------- 2 files changed, 41 insertions(+), 74 deletions(-) (limited to 'src') diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index b1751c0ae..ebd7b7cbb 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -47,49 +47,45 @@ using namespace std; using namespace TheISA; using namespace ThePipeline; -InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, - const TheISA::PCState &instPC, - const TheISA::PCState &_predPC, - InstSeqNum seq_num, InOrderCPU *cpu) - : staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu) -{ - seqNum = seq_num; - - pc = instPC; - predPC = _predPC; - - initVars(); -} - InOrderDynInst::InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num, ThreadID tid, unsigned _asid) - : traceData(NULL), cpu(cpu) -{ - seqNum = seq_num; - thread = state; - threadNumber = tid; - asid = _asid; - initVars(); -} + : seqNum(seq_num), bdelaySeqNum(0), threadNumber(tid), asid(_asid), + virtProcNumber(0), staticInst(NULL), traceData(NULL), cpu(cpu), + thread(state), fault(NoFault), memData(NULL), loadData(0), + storeData(0), effAddr(0), physEffAddr(0), memReqFlags(0), + readyRegs(0), pc(0), predPC(0), memAddr(0), nextStage(0), + memTime(0), splitMemData(NULL), splitMemReq(NULL), totalSize(0), + split2ndSize(0), split2ndAddr(0), split2ndAccess(false), + split2ndDataPtr(NULL), split2ndFlags(0), splitInst(false), + splitFinishCnt(0), split2ndStoreDataPtr(NULL), splitInstSked(false), + inFrontEnd(true), frontSked(NULL), backSked(NULL), + squashingStage(0), predictTaken(false), procDelaySlotOnMispred(false), + fetchMemReq(NULL), dataMemReq(NULL), instEffAddr(0), eaCalcDone(false), + lqIdx(0), sqIdx(0), instListIt(NULL) +{ + for(int i = 0; i < MaxInstSrcRegs; i++) { + instSrc[i].integer = 0; + instSrc[i].dbl = 0; + _readySrcRegIdx[i] = false; + _srcRegIdx[i] = 0; + } -InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst) - : seqNum(0), staticInst(_staticInst), traceData(NULL) -{ - initVars(); -} + for(int j = 0; j < MaxInstDestRegs; j++) { + _destRegIdx[j] = 0; + _prevDestRegIdx[j] = 0; + } + + ++instcount; + DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created." + " (active insts: %i)\n", threadNumber, seqNum, instcount); -InOrderDynInst::InOrderDynInst() - : seqNum(0), traceData(NULL), cpu(cpu) -{ - initVars(); } int InOrderDynInst::instcount = 0; - void InOrderDynInst::setMachInst(ExtMachInst machInst) { @@ -133,7 +129,6 @@ InOrderDynInst::initVars() memAddrReady = false; eaCalcDone = false; - memOpDone = false; predictTaken = false; procDelaySlotOnMispred = false; @@ -164,16 +159,10 @@ InOrderDynInst::initVars() } // Update Instruction Count for this instruction - ++instcount; if (instcount > 100) { fatal("Number of Active Instructions in CPU is too high. " "(Not Dereferencing Ptrs. Correctly?)\n"); } - - - - DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created." - " (active insts: %i)\n", threadNumber, seqNum, instcount); } void diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 0e6be3da2..04f9abb96 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -106,17 +106,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted }; public: - /** BaseDynInst constructor given a binary instruction. - * @param inst The binary instruction. - * @param PC The PC of the instruction. - * @param predPC The predicted next PC. - * @param seq_num The sequence number of the instruction. - * @param cpu Pointer to the instruction's CPU. - */ - InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC, - const TheISA::PCState &predPC, InstSeqNum seq_num, - InOrderCPU *cpu); - /** BaseDynInst constructor given a binary instruction. * @param seq_num The sequence number of the instruction. * @param cpu Pointer to the instruction's CPU. @@ -125,14 +114,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num, ThreadID tid, unsigned asid = 0); - /** BaseDynInst constructor given a StaticInst pointer. - * @param _staticInst The StaticInst for this BaseDynInst. - */ - InOrderDynInst(StaticInstPtr &_staticInst); - - /** Skeleton Constructor. */ - InOrderDynInst(); - /** InOrderDynInst destructor. */ ~InOrderDynInst(); @@ -219,12 +200,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** The effective physical address. */ Addr physEffAddr; - /** Effective virtual address for a copy source. */ - Addr copySrcEffAddr; - - /** Effective physical address for a copy source. */ - Addr copySrcPhysEffAddr; - /** The memory request flags (from translation). */ unsigned memReqFlags; @@ -253,8 +228,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted Tick tick; InstResult() - : type(None), tick(0) - {} + : type(None), tick(0) + { + val.integer = 0; + val.dbl = 0; + } }; /** The source of the instruction; assumes for now that there's only one @@ -273,10 +251,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Predicted next PC. */ TheISA::PCState predPC; - /** Address to fetch from */ - Addr fetchAddr; - /** Address to get/write data from/to */ + /* Fetching address when inst. starts, Data address for load/store after fetch*/ Addr memAddr; /** Whether or not the source register is ready. @@ -477,7 +453,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted curSkedEntry++; if (inFrontEnd && curSkedEntry == frontSked_end) { - assert(backSked != NULL); + DPRINTF(InOrderDynInst, "[sn:%i] Switching to " + "back end schedule.\n", seqNum); + assert(backSked != NULL); curSkedEntry.init(backSked); curSkedEntry = backSked->begin(); inFrontEnd = false; @@ -485,6 +463,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted return true; } + DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i " + "Next Resource: %i.\n", seqNum, curSkedEntry->stageNum, + curSkedEntry->resNum); + return false; } @@ -996,10 +978,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted */ bool eaCalcDone; - public: - /** Whether or not the memory operation is done. */ - bool memOpDone; - public: /** Load queue index. */ int16_t lqIdx; -- cgit v1.2.3