From 53c241fc16e4edaae8440b3dd360503537dbaba3 Mon Sep 17 00:00:00 2001 From: Joel Hestness Date: Thu, 12 Aug 2010 17:16:02 -0700 Subject: TimingSimpleCPU: fix NO_ACCESS memory op handling When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse --- src/cpu/simple/timing.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index b8fc5ab84..8a53aac3a 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -868,6 +868,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) // received a response from the dcache: complete the load or store // instruction assert(!pkt->isError()); + assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || + pkt->req->getFlags().isSet(Request::NO_ACCESS)); numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; @@ -897,7 +899,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) } } - assert(_status == DcacheWaitResponse || _status == DTBWaitResponse); _status = Running; Fault fault = curStaticInst->completeAcc(pkt, this, traceData); -- cgit v1.2.3