From 53e777d6838ac3ca80e6557626f9e99fd93dd0f7 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Fri, 7 Aug 2015 09:59:13 +0100 Subject: base: Declare a type for context IDs Context IDs used to be declared as ad hoc (usually as int). This changeset introduces a typedef for ContextIDs and a constant for invalid context IDs. --- src/base/types.hh | 4 ++++ src/cpu/base_dyn_inst.hh | 2 +- src/cpu/checker/thread_context.hh | 4 ++-- src/cpu/minor/exec_context.hh | 2 +- src/cpu/o3/thread_context.hh | 2 +- src/cpu/thread_context.cc | 6 +++--- src/cpu/thread_state.hh | 6 +++--- src/dev/arm/gic_pl390.cc | 10 +++++----- src/dev/arm/gic_pl390.hh | 2 +- src/dev/arm/timer_cpulocal.cc | 4 ++-- src/dev/arm/vgic.cc | 10 +++++----- src/dev/arm/vgic.hh | 2 +- src/dev/sinic.cc | 12 ++++++------ src/dev/sinic.hh | 8 ++++---- src/dev/sparc/iob.cc | 4 ++-- src/mem/abstract_mem.hh | 2 +- src/mem/cache/blk.hh | 2 +- src/mem/cache/cache_impl.hh | 3 ++- src/mem/physical.cc | 4 ++-- src/mem/request.hh | 8 ++++---- src/mem/ruby/slicc_interface/RubyRequest.hh | 4 ++-- src/mem/ruby/system/Sequencer.cc | 6 ++---- src/sim/process.hh | 4 ++-- src/sim/system.cc | 8 ++++---- src/sim/system.hh | 7 ++++--- 25 files changed, 65 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/src/base/types.hh b/src/base/types.hh index 3d53e6ba0..bc5c715ce 100644 --- a/src/base/types.hh +++ b/src/base/types.hh @@ -181,6 +181,10 @@ const Addr MaxAddr = (Addr)-1; typedef int16_t ThreadID; const ThreadID InvalidThreadID = (ThreadID)-1; +/** Globally unique thread context ID */ +typedef int ContextID; +const ContextID InvalidContextID = (ContextID)-1; + /** * Port index/ID type, and a symbolic name for an invalid port id. */ diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 5b54679c9..aae3af495 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -460,7 +460,7 @@ class BaseDynInst : public ExecContext, public RefCounted MasterID masterId() const { return cpu->dataMasterId(); } /** Read this context's system-wide ID **/ - int contextId() const { return thread->contextId(); } + ContextID contextId() const { return thread->contextId(); } /** Returns the fault type. */ Fault getFault() const { return fault; } diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 71c231ba0..5fcb82f6d 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -96,9 +96,9 @@ class CheckerThreadContext : public ThreadContext int cpuId() const { return actualTC->cpuId(); } - int contextId() const { return actualTC->contextId(); } + ContextID contextId() const { return actualTC->contextId(); } - void setContextId(int id) + void setContextId(ContextID id) { actualTC->setContextId(id); checkerTC->setContextId(id); diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 80d5d9872..3e4ea5ea9 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -254,7 +254,7 @@ class ExecContext : public ::ExecContext unsigned int readStCondFailures() const { return 0; } void setStCondFailures(unsigned int st_cond_failures) {} - int contextId() { return thread.contextId(); } + ContextID contextId() { return thread.contextId(); } /* ISA-specific (or at least currently ISA singleton) functions */ /* X86: TLB twiddling */ diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 87d87900c..87b7d9198 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -101,7 +101,7 @@ class O3ThreadContext : public ThreadContext /** Reads this CPU's Socket ID. */ virtual uint32_t socketId() const { return cpu->socketId(); } - virtual int contextId() const { return thread->contextId(); } + virtual ContextID contextId() const { return thread->contextId(); } virtual void setContextId(int id) { thread->setContextId(id); } diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index fe1ae69dd..01ea51f26 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -95,9 +95,9 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) if (id1 != id2) panic("CPU ids don't match, one: %d, two: %d", id1, id2); - id1 = one->contextId(); - id2 = two->contextId(); - if (id1 != id2) + const ContextID cid1 = one->contextId(); + const ContextID cid2 = two->contextId(); + if (cid1 != cid2) panic("Context ids don't match, one: %d, two: %d", id1, id2); diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 485c9306f..bd471e13a 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -71,9 +71,9 @@ struct ThreadState : public Serializable { uint32_t socketId() const { return baseCpu->socketId(); } - int contextId() const { return _contextId; } + ContextID contextId() const { return _contextId; } - void setContextId(int id) { _contextId = id; } + void setContextId(ContextID id) { _contextId = id; } void setThreadId(ThreadID id) { _threadId = id; } @@ -153,7 +153,7 @@ struct ThreadState : public Serializable { BaseCPU *baseCpu; // system wide HW context id - int _contextId; + ContextID _contextId; // Index of hardware thread context on the CPU that this represents. ThreadID _threadId; diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc index 5a21f6cec..fb1711c92 100644 --- a/src/dev/arm/gic_pl390.cc +++ b/src/dev/arm/gic_pl390.cc @@ -135,7 +135,7 @@ Pl390::readDistributor(PacketPtr pkt) { Addr daddr = pkt->getAddr() - distAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(GIC, "gic distributor read register %#x\n", daddr); @@ -269,7 +269,7 @@ Pl390::readCpu(PacketPtr pkt) Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < sys->numRunningContexts()); DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr, @@ -356,7 +356,7 @@ Pl390::writeDistributor(PacketPtr pkt) Addr daddr = pkt->getAddr() - distAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); uint32_t pkt_data M5_VAR_USED; switch (pkt->getSize()) @@ -496,7 +496,7 @@ Pl390::writeCpu(PacketPtr pkt) Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); IAR iar; DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n", @@ -546,7 +546,7 @@ Pl390::writeCpu(PacketPtr pkt) } void -Pl390::softInt(int ctx_id, SWI swi) +Pl390::softInt(ContextID ctx_id, SWI swi) { switch (swi.list_type) { case 1: diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index 1adad6c9a..17946145f 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -210,7 +210,7 @@ class Pl390 : public BaseGic /** software generated interrupt * @param data data to decode that indicates which cpus to interrupt */ - void softInt(int ctx_id, SWI swi); + void softInt(ContextID ctx_id, SWI swi); /** See if some processor interrupt flags need to be enabled/disabled * @param hint which set of interrupts needs to be checked diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc index ac02d099f..11ae3b3d2 100644 --- a/src/dev/arm/timer_cpulocal.cc +++ b/src/dev/arm/timer_cpulocal.cc @@ -75,7 +75,7 @@ CpuLocalTimer::read(PacketPtr pkt) assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); @@ -153,7 +153,7 @@ CpuLocalTimer::write(PacketPtr pkt) assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc index f4a3e8c3f..71d1d3bb6 100644 --- a/src/dev/arm/vgic.cc +++ b/src/dev/arm/vgic.cc @@ -90,7 +90,7 @@ VGic::readVCpu(PacketPtr pkt) { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -134,7 +134,7 @@ VGic::readCtrl(PacketPtr pkt) { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); @@ -228,7 +228,7 @@ VGic::writeVCpu(PacketPtr pkt) { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -275,7 +275,7 @@ VGic::writeCtrl(PacketPtr pkt) { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get()); @@ -380,7 +380,7 @@ VGic::unPostMaintInt(uint32_t cpu) * This may raise a maintenance interrupt. */ void -VGic::updateIntState(int ctx_id) +VGic::updateIntState(ContextID ctx_id) { // @todo This should update APRs! diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh index ac88f842f..d44afd7a9 100644 --- a/src/dev/arm/vgic.hh +++ b/src/dev/arm/vgic.hh @@ -222,7 +222,7 @@ class VGic : public PioDevice Tick writeVCpu(PacketPtr pkt); Tick writeCtrl(PacketPtr pkt); - void updateIntState(int ctx_id); + void updateIntState(ContextID ctx_id); uint32_t getMISR(struct vcpuIntData *vid); void postVInt(uint32_t cpu, Tick when); void unPostVInt(uint32_t cpu); diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index d4a3f19b3..a17f50864 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -152,7 +152,7 @@ Device::getEthPort(const std::string &if_name, int idx) void -Device::prepareIO(int cpu, int index) +Device::prepareIO(ContextID cpu, int index) { int size = virtualRegs.size(); if (index > size) @@ -165,7 +165,7 @@ Device::prepareIO(int cpu, int index) //add stats for average number of vnics busy void -Device::prepareRead(int cpu, int index) +Device::prepareRead(ContextID cpu, int index) { using namespace Regs; prepareIO(cpu, index); @@ -206,7 +206,7 @@ Device::prepareRead(int cpu, int index) } void -Device::prepareWrite(int cpu, int index) +Device::prepareWrite(ContextID cpu, int index) { prepareIO(cpu, index); } @@ -220,7 +220,7 @@ Device::read(PacketPtr pkt) assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -270,7 +270,7 @@ Device::read(PacketPtr pkt) * IPR read of device register Fault -Device::iprRead(Addr daddr, int cpu, uint64_t &result) +Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result) { if (!regValid(daddr)) panic("invalid address: da=%#x", daddr); @@ -305,7 +305,7 @@ Device::write(PacketPtr pkt) assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 69b81b1b2..f0645a807 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -273,10 +273,10 @@ class Device : public Base virtual Tick write(PacketPtr pkt); virtual void drainResume() M5_ATTR_OVERRIDE; - void prepareIO(int cpu, int index); - void prepareRead(int cpu, int index); - void prepareWrite(int cpu, int index); - // Fault iprRead(Addr daddr, int cpu, uint64_t &result); + void prepareIO(ContextID cpu, int index); + void prepareRead(ContextID cpu, int index); + void prepareWrite(ContextID cpu, int index); + // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result); /** * Statistics diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index bee0323c8..c8462b9be 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -118,7 +118,7 @@ void Iob::readJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; @@ -233,7 +233,7 @@ void Iob::writeJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh index 4b7ad8139..6dbc79ea0 100644 --- a/src/mem/abstract_mem.hh +++ b/src/mem/abstract_mem.hh @@ -74,7 +74,7 @@ class LockedAddr { Addr addr; // locking hw context - const int contextId; + const ContextID contextId; static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index 0be22f45d..2b3a34bb8 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -130,7 +130,7 @@ class CacheBlk */ class Lock { public: - int contextId; // locking context + ContextID contextId; // locking context Addr lowAddr; // low address of lock range Addr highAddr; // high address of lock range diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 62ab49538..dea95d955 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -332,7 +332,8 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, return false; } - int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + ContextID id = pkt->req->hasContextId() ? + pkt->req->contextId() : InvalidContextID; // Here lat is the value passed as parameter to accessBlock() function // that can modify its value. blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); diff --git a/src/mem/physical.cc b/src/mem/physical.cc index d757b8c5d..dfea2e9e1 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -293,7 +293,7 @@ PhysicalMemory::serialize(CheckpointOut &cp) const { // serialize all the locked addresses and their context ids vector lal_addr; - vector lal_cid; + vector lal_cid; for (auto& m : memories) { const list& locked_addrs = m->getLockedAddrList(); @@ -370,7 +370,7 @@ PhysicalMemory::unserialize(CheckpointIn &cp) // unserialize the locked addresses and map them to the // appropriate memory controller vector lal_addr; - vector lal_cid; + vector lal_cid; UNSERIALIZE_CONTAINER(lal_addr); UNSERIALIZE_CONTAINER(lal_cid); for(size_t i = 0; i < lal_addr.size(); ++i) { diff --git a/src/mem/request.hh b/src/mem/request.hh index 192b4c89f..0e2ece857 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -296,7 +296,7 @@ class Request uint64_t _extraData; /** The context ID (for statistics, typically). */ - int _contextId; + ContextID _contextId; /** The thread ID (id within this CPU) */ ThreadID _threadId; @@ -353,7 +353,7 @@ class Request } Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, - Addr pc, int cid, ThreadID tid) + Addr pc, ContextID cid, ThreadID tid) : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), _extraData(0), _contextId(0), _threadId(0), _pc(0), @@ -369,7 +369,7 @@ class Request * Set up CPU and thread numbers. */ void - setThreadContext(int context_id, ThreadID tid) + setThreadContext(ContextID context_id, ThreadID tid) { _contextId = context_id; _threadId = tid; @@ -591,7 +591,7 @@ class Request } /** Accessor function for context ID.*/ - int + ContextID contextId() const { assert(privateFlags.isSet(VALID_CONTEXT_ID)); diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh index 357eddbb5..cdb04bceb 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.hh +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh @@ -49,12 +49,12 @@ class RubyRequest : public Message PrefetchBit m_Prefetch; uint8_t* data; PacketPtr pkt; - unsigned m_contextId; + ContextID m_contextId; RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, - unsigned _proc_id = 100) + ContextID _proc_id = 100) : Message(curTime), m_PhysicalAddress(_paddr), m_Type(_type), diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 32e4c107c..01b868017 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -667,10 +667,8 @@ void Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) { assert(pkt != NULL); - int proc_id = -1; - if (pkt->req->hasContextId()) { - proc_id = pkt->req->contextId(); - } + ContextID proc_id = pkt->req->hasContextId() ? + pkt->req->contextId() : InvalidContextID; // If valid, copy the pc to the ruby request Addr pc = 0; diff --git a/src/sim/process.hh b/src/sim/process.hh index 82a84a935..f509b81c7 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -75,7 +75,7 @@ class Process : public SimObject System *system; // thread contexts associated with this process - std::vector contextIds; + std::vector contextIds; // number of CPUs (esxec contexts, really) assigned to this process. unsigned int numCpus() { return contextIds.size(); } @@ -160,7 +160,7 @@ class Process : public SimObject // After getting registered with system object, tell process which // system-wide context id it is assigned. - void assignThreadContext(int context_id) + void assignThreadContext(ContextID context_id) { contextIds.push_back(context_id); } diff --git a/src/sim/system.cc b/src/sim/system.cc index c5e2e0b96..d0418d99b 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -209,11 +209,11 @@ bool System::breakpoint() */ int rgdb_wait = -1; -int -System::registerThreadContext(ThreadContext *tc, int assigned) +ContextID +System::registerThreadContext(ThreadContext *tc, ContextID assigned) { int id; - if (assigned == -1) { + if (assigned == InvalidContextID) { for (id = 0; id < threadContexts.size(); id++) { if (!threadContexts[id]) break; @@ -305,7 +305,7 @@ System::initState() } void -System::replaceThreadContext(ThreadContext *tc, int context_id) +System::replaceThreadContext(ThreadContext *tc, ContextID context_id) { if (context_id >= threadContexts.size()) { panic("replaceThreadContext: bad id, %d >= %d\n", diff --git a/src/sim/system.hh b/src/sim/system.hh index 97d271d3a..634c78a6a 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -197,7 +197,7 @@ class System : public MemObject std::vector threadContexts; int _numContexts; - ThreadContext *getThreadContext(ThreadID tid) + ThreadContext *getThreadContext(ContextID tid) { return threadContexts[tid]; } @@ -514,8 +514,9 @@ class System : public MemObject /// @return Starting address of first page Addr allocPhysPages(int npages); - int registerThreadContext(ThreadContext *tc, int assigned=-1); - void replaceThreadContext(ThreadContext *tc, int context_id); + ContextID registerThreadContext(ThreadContext *tc, + ContextID assigned = InvalidContextID); + void replaceThreadContext(ThreadContext *tc, ContextID context_id); void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; -- cgit v1.2.3