From 556ea0ee571a20352856217427ec42e337ea4734 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 2 Jun 2010 12:58:13 -0500
Subject: ARM: Add some support for wfi/wfe/yield/etc

---
 src/arch/arm/isa.hh              |  3 +++
 src/arch/arm/isa/decoder/arm.isa | 25 +++++++++++++++++++++----
 src/arch/arm/isa/includes.isa    |  1 +
 src/arch/arm/isa/operands.isa    |  1 +
 src/arch/arm/miscregs.hh         |  3 ++-
 5 files changed, 28 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index ded463267..2d6a97fb6 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -119,6 +119,9 @@ namespace ArmISA
             /* One region, unified map. */
             miscRegs[MISCREG_MPUIR] = 0x100;
 
+            /* Start with an event in the mailbox */
+            miscRegs[MISCREG_SEV_MAILBOX] = 1;
+
             /*
              * Implemented = '5' from "M5",
              * Variant = 0,
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 4c5d71ad9..f453d8299 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -86,10 +86,27 @@ format DataOp {
             0x9: decode RN {
                 0: decode IMM {
                     0: PredImmOp::nop({{ ; }});
-                    1: WarnUnimpl::yield();
-                    2: WarnUnimpl::wfe();
-                    3: WarnUnimpl::wfi();
-                    4: WarnUnimpl::sev();
+#if FULL_SYSTEM
+                    1: PredImmOp::yield({{ ; }});
+                    2: PredImmOp::wfe({{
+                        if (SevMailbox)
+                            SevMailbox = 0;
+                        else
+                            PseudoInst::quiesce(xc->tcBase());
+                    }}, IsNonSpeculative, IsQuiesce);
+                    3: PredImmOp::wfi({{
+                            PseudoInst::quiesce(xc->tcBase());
+                    }}, IsNonSpeculative, IsQuiesce);
+                    4: PredImmOp::sev({{
+                        // Need a way for O3 to not scoreboard these
+                        // accesses as pipeflushs
+                        System *sys = xc->tcBase()->getSystemPtr();
+                        for (int x = 0; x < sys->numContexts(); x++) {
+                            ThreadContext *oc = sys->getThreadContext(x);
+                            oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+                        }
+                    }});
+#endif
                 }
                 default: PredImmOp::msr_i_cpsr({{
                             uint32_t newCpsr =
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 72c2e559a..c20b16724 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -76,6 +76,7 @@ output exec {{
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 #include "base/condcodes.hh"
+#include "sim/pseudo_inst.hh"
 
 #include <cmath>
 #if defined(linux)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 53a0e78f9..9f4a0ca2f 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -176,6 +176,7 @@ def operands {{
     'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
     'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
+    'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
             readNPC, writeNPC),
     'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index e3e2ca2c2..81a448fd2 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -80,6 +80,7 @@ namespace ArmISA
         MISCREG_FPEXC,
         MISCREG_MVFR0,
         MISCREG_MVFR1,
+        MISCREG_SEV_MAILBOX,
 
         // CP15 registers
         MISCREG_CP15_START,
@@ -159,7 +160,7 @@ namespace ArmISA
     const char * const miscRegName[NUM_MISCREGS] = {
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
-        "fpsr", "fpsid", "fpscr", "fpexc",
+        "fpsr", "fpsid", "fpscr", "fpexc", "sev_mailbox",
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
-- 
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