From 5ea60a95b3d87fac6723678e07822aed512f966e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 3 Feb 2015 14:25:52 -0500 Subject: config: Adjust DRAM channel interleaving defaults This patch changes the DRAM channel interleaving default behaviour to be more representative. The default address mapping (RoRaBaCoCh) moves the channel bits towards the least significant bits, and uses 128 byte as the default channel interleaving granularity. These defaults can be overridden if desired, but should serve as a sensible starting point for most use-cases. --- src/mem/DRAMCtrl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 4c500960a..60b3b251e 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -92,7 +92,7 @@ class DRAMCtrl(AbstractMemory): # scheduler, address map and page policy mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") - addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") + addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") page_policy = Param.PageManage('open_adaptive', "Page management policy") # enforce a limit on the number of accesses per row -- cgit v1.2.3