From 6fb5189c47546fe97fb66550f5484f4d96c4397b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:10 -0500
Subject: ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.

---
 src/arch/arm/isa/formats/misc.isa |  9 +++++++++
 src/arch/arm/miscregs.hh          | 11 ++++++-----
 2 files changed, 15 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 8d386b0b0..d01b5014d 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -128,6 +128,15 @@ def format McrMrc15() {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+          case MISCREG_DRBAR:
+            return new WarnUnimplemented(
+                    isRead ? "mrc drbar" : "mcr drbar", machInst);
+          case MISCREG_DRACR:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dracr" : "mcr dracr", machInst);
+          case MISCREG_DRSR:
+            return new WarnUnimplemented(
+                    isRead ? "mrc drsr" : "mcr drsr", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 914ca6242..704450d1c 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -105,6 +105,9 @@ namespace ArmISA
         MISCREG_MPUIR,
         MISCREG_MIDR,
         MISCREG_RGNR,
+        MISCREG_DRBAR,
+        MISCREG_DRACR,
+        MISCREG_DRSR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -131,11 +134,8 @@ namespace ArmISA
         MISCREG_AIFSR,
         MISCREG_DFAR,
         MISCREG_IFAR,
-        MISCREG_DRBAR,
         MISCREG_IRBAR,
-        MISCREG_DRSR,
         MISCREG_IRSR,
-        MISCREG_DRACR,
         MISCREG_IRACR,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
@@ -164,13 +164,14 @@ namespace ArmISA
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "mpuir", "midr", "rgnr", "ctr", "tcmtr", "mpidr",
+        "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
+        "ctr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
         "aidr", "actlr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
-        "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
+        "irbar", "irsr", "iracr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nop", "raz"
-- 
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