From 74305fad328ad22fa3bf32b50ad683043494803c Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 9 Feb 2018 11:31:05 +0000 Subject: arch-arm: ERET from AArch64 to AArch32 ignore MSBs The 32 most significant bits of ELR_ELx must be ignored when returning from AArch64 to AArch32. Change-Id: I412d72908997916404e16e9eeca2789a9c529e58 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/8881 Maintainer: Andreas Sandberg --- src/arch/arm/isa/insts/branch64.isa | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa index 64457b8c0..8ef9f934e 100644 --- a/src/arch/arm/isa/insts/branch64.isa +++ b/src/arch/arm/isa/insts/branch64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013, 2016 ARM Limited +// Copyright (c) 2011-2013, 2016,2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -120,12 +120,19 @@ let {{ mnemonic); break; } - if (spsr.width && (newPc & mask(2))) { - // To avoid PC Alignment fault when returning to AArch32 - if (spsr.t) - newPc = newPc & ~mask(1); - else - newPc = newPc & ~mask(2); + if (spsr.width) { + // Exception return to AArch32. + // 32 most significant bits are ignored + newPc &= mask(32); + + if (newPc & mask(2)) { + // Mask bits to avoid PC Alignment fault when returning + // to AArch32 + if (spsr.t) + newPc = newPc & ~mask(1); + else + newPc = newPc & ~mask(2); + } } CPSR new_cpsr = getPSTATEFromPSR(xc->tcBase(), cpsr, spsr); -- cgit v1.2.3