From 748b87fc368800495e5906428bf748359d6bf19a Mon Sep 17 00:00:00 2001
From: Brandon Potter <brandon.potter@amd.com>
Date: Thu, 23 Feb 2017 13:27:48 -0500
Subject: x86: remove redundant condition check in tlb code

---
 src/arch/x86/tlb.cc | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index a5e8f5524..191e91a00 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -231,13 +231,10 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
     AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
 
     if (m5opRange.contains(paddr)) {
-        if (m5opRange.contains(paddr)) {
-            req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
-                          Request::STRICT_ORDER);
-            req->setPaddr(GenericISA::iprAddressPseudoInst(
-                            (paddr >> 8) & 0xFF,
-                            paddr & 0xFF));
-        }
+        req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
+                      Request::STRICT_ORDER);
+        req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
+                                                       paddr & 0xFF));
     } else if (FullSystem) {
         // Check for an access to the local APIC
         LocalApicBase localApicBase =
-- 
cgit v1.2.3