From 7645c8e611b5530b82789246b5025558f4b1a422 Mon Sep 17 00:00:00 2001 From: Neha Agarwal Date: Fri, 1 Nov 2013 11:56:21 -0400 Subject: mem: Fix for 100% write threshold in DRAM controller This patch fixes the controller when a write threshold of 100% is used. Earlier for 100% write threshold no data is written to memory as writes never get triggered since this corner case is not considered. --- src/mem/simple_dram.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc index 9cbca6a1c..9669c7a03 100644 --- a/src/mem/simple_dram.cc +++ b/src/mem/simple_dram.cc @@ -563,7 +563,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) accessAndRespond(pkt, frontendLatency); // If your write buffer is starting to fill up, drain it! - if (writeQueue.size() > writeThreshold && !stopReads){ + if (writeQueue.size() >= writeThreshold && !stopReads){ triggerWrites(); } } -- cgit v1.2.3