From 789153dff64edcf046d800f231dffa6d66004ed5 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Thu, 15 Nov 2007 03:10:41 -0500 Subject: Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" --HG-- extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea --- src/arch/alpha/regfile.hh | 3 --- src/arch/isa_parser.py | 37 ++++++++++++++++++++++++++++++++++ src/arch/mips/faults.cc | 2 +- src/arch/mips/isa/decoder.isa | 4 ++-- src/cpu/o3/thread_context.hh | 5 ++--- src/cpu/o3/thread_context_impl.hh | 42 +++------------------------------------ src/cpu/simple/base.cc | 4 ++-- src/cpu/simple/base.hh | 6 +----- src/cpu/simple_thread.hh | 4 ---- src/cpu/thread_context.hh | 14 ++++--------- 10 files changed, 52 insertions(+), 69 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 8a150dc69..792a518fb 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -177,9 +177,6 @@ namespace AlphaISA intRegFile.setReg(intReg, val); } - void setShadowSet(int css) - { } - void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index ef21f7ceb..bbdd95bb0 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1235,6 +1235,9 @@ class Operand(object): def isControlReg(self): return 0 + def isIControlReg(self): + return 0 + def getFlags(self): # note the empty slice '[:]' gives us a copy of self.flags[0] # instead of a reference to it @@ -1610,6 +1613,8 @@ def buildOperandNameMap(userDict, lineno): global operandsWithExtRE operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE) +maxInstSrcRegs = 0 +maxInstDestRegs = 0 class OperandList: @@ -1673,6 +1678,12 @@ class OperandList: if self.memOperand: error(0, "Code block has more than one memory operand.") self.memOperand = op_desc + global maxInstSrcRegs + global maxInstDestRegs + if maxInstSrcRegs < self.numSrcRegs: + maxInstSrcRegs = self.numSrcRegs + if maxInstDestRegs < self.numDestRegs: + maxInstDestRegs = self.numDestRegs # now make a final pass to finalize op_desc fields that may depend # on the register enumeration for op_desc in self.items: @@ -1892,6 +1903,22 @@ namespace %(namespace)s { %(decode_function)s ''' +max_inst_regs_template = ''' +/* + * DO NOT EDIT THIS FILE!!! + * + * It was automatically generated from the ISA description in %(filename)s + */ + +namespace %(namespace)s { + + const int MaxInstSrcRegs = %(MaxInstSrcRegs)d; + const int MaxInstDestRegs = %(MaxInstDestRegs)d; + +} // namespace %(namespace)s + +''' + # Update the output file only if the new contents are different from # the current contents. Minimizes the files that need to be rebuilt @@ -1991,6 +2018,16 @@ def parse_isa_desc(isa_desc_file, output_dir): update_if_needed(output_dir + '/' + cpu.filename, file_template % vars()) + # The variable names here are hacky, but this will creat local variables + # which will be referenced in vars() which have the value of the globals. + global maxInstSrcRegs + MaxInstSrcRegs = maxInstSrcRegs + global maxInstDestRegs + MaxInstDestRegs = maxInstDestRegs + # max_inst_regs.hh + update_if_needed(output_dir + '/max_inst_regs.hh', \ + max_inst_regs_template % vars()) + # global list of CpuModel objects (see cpu_models.py) cpu_models = [] diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 3e1cb69c9..b2778dcd0 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -196,7 +196,7 @@ void MipsFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode) // Move ESS to CSS replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS); tc->setMiscRegNoEffect(MipsISA::SRSCtl,srs); - tc->setShadowSet(ESS); + //tc->setShadowSet(ESS); } // set EXL bit (don't care if it is already set!) diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index eb1b0390a..9a2641138 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -652,7 +652,7 @@ decode OPCODE_HI default Unknown::unknown() { Status_EXL = 0; if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){ SRSCtl_CSS = SRSCtl_PSS; - xc->setShadowSet(SRSCtl_PSS); + //xc->setShadowSet(SRSCtl_PSS); } } LLFlag = 0; @@ -2086,7 +2086,7 @@ decode OPCODE_HI default Unknown::unknown() { format CP0Control { 0x7: cache({{ Addr CacheEA = Rs.uw + OFFSET; - fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); + //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); }}); } } diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 24745735f..44ff8da8a 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -117,13 +117,13 @@ class O3ThreadContext : public ThreadContext virtual void activate(int delay = 1); /** Set the status to Suspended. */ - virtual void suspend(); + virtual void suspend(int delay = 0); /** Set the status to Unallocated. */ virtual void deallocate(int delay = 0); /** Set the status to Halted. */ - virtual void halt(); + virtual void halt(int delay = 0); #if FULL_SYSTEM /** Dumps the function profiling information. @@ -236,7 +236,6 @@ class O3ThreadContext : public ThreadContext * misspeculating, this is set as false. */ virtual bool misspeculating() { return false; } - virtual void setShadowSet(int ss) { }; #if !FULL_SYSTEM /** Gets a syscall argument by index. */ virtual IntReg getSyscallArg(int i); diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 55584629e..2d329b056 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -136,7 +136,7 @@ O3ThreadContext::activate(int delay) template void -O3ThreadContext::suspend() +O3ThreadContext::suspend(int delay) { DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", getThreadNum()); @@ -177,7 +177,7 @@ O3ThreadContext::deallocate(int delay) template void -O3ThreadContext::halt() +O3ThreadContext::halt(int delay) { DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", getThreadNum()); @@ -289,13 +289,9 @@ O3ThreadContext::copyArchRegs(ThreadContext *tc) // Copy the misc regs. TheISA::copyMiscRegs(tc, this); - // Then finally set the PC, the next PC, the nextNPC, the micropc, and the - // next micropc. + // Then finally set the PC and the next PC. cpu->setPC(tc->readPC(), tid); cpu->setNextPC(tc->readNextPC(), tid); - cpu->setNextNPC(tc->readNextNPC(), tid); - cpu->setMicroPC(tc->readMicroPC(), tid); - cpu->setNextMicroPC(tc->readNextMicroPC(), tid); #if !FULL_SYSTEM this->thread->funcExeInst = tc->readFuncExeInst(); #endif @@ -318,7 +314,6 @@ template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); @@ -334,7 +329,6 @@ template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } @@ -343,7 +337,6 @@ TheISA::FloatRegBits O3ThreadContext::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -351,7 +344,6 @@ template TheISA::FloatRegBits O3ThreadContext::readFloatRegBits(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -372,7 +364,6 @@ template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -392,7 +383,6 @@ template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); if (!thread->trapPending && !thread->inSyscall) { @@ -406,7 +396,6 @@ O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. @@ -419,7 +408,6 @@ template void O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. @@ -452,30 +440,6 @@ O3ThreadContext::setNextPC(uint64_t val) } } -template -void -O3ThreadContext::setMicroPC(uint64_t val) -{ - cpu->setMicroPC(val, thread->readTid()); - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); - } -} - -template -void -O3ThreadContext::setNextMicroPC(uint64_t val) -{ - cpu->setNextMicroPC(val, thread->readTid()); - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->readTid()); - } -} - template void O3ThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index e521837df..010c21e4a 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -503,7 +503,7 @@ BaseSimpleCPU::advancePC(Fault fault) } while (oldpc != thread->readPC()); } -Fault +/*Fault BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) { // translate to physical address @@ -536,4 +536,4 @@ BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) } } return fault; -} +}*/ diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 5990e46b0..82f73e5dd 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -378,12 +378,8 @@ class BaseSimpleCPU : public BaseCPU "register access.\n"); } - void setShadowSet(int css) { - panic("Simple CPU models do not support Shadow Sets"); - //tc->setShadowSet(css); - } + //Fault CacheOp(uint8_t Op, Addr EA); - Fault CacheOp(uint8_t Op, Addr EA); #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } void ev5_trap(Fault fault) { fault->invoke(tc); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index cccb53322..2b79c9708 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -368,10 +368,6 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } - void setShadowSet(int css, int tid=0) { - regs.setShadowSet(css); - } - #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index fd35efc91..9f6af8890 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -150,13 +150,13 @@ class ThreadContext virtual void activate(int delay = 1) = 0; /// Set the status to Suspended. - virtual void suspend() = 0; + virtual void suspend(int delay = 0) = 0; /// Set the status to Unallocated. virtual void deallocate(int delay = 0) = 0; /// Set the status to Halted. - virtual void halt() = 0; + virtual void halt(int delay = 0) = 0; #if FULL_SYSTEM virtual void dumpFuncProfile() = 0; @@ -238,8 +238,6 @@ class ThreadContext virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; - virtual void setShadowSet(int css) = 0; - // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() = 0; @@ -335,13 +333,13 @@ class ProxyThreadContext : public ThreadContext void activate(int delay = 1) { actualTC->activate(delay); } /// Set the status to Suspended. - void suspend() { actualTC->suspend(); } + void suspend(int delay = 0) { actualTC->suspend(); } /// Set the status to Unallocated. void deallocate(int delay = 0) { actualTC->deallocate(); } /// Set the status to Halted. - void halt() { actualTC->halt(); } + void halt(int delay = 0) { actualTC->halt(); } #if FULL_SYSTEM void dumpFuncProfile() { actualTC->dumpFuncProfile(); } @@ -409,10 +407,6 @@ class ProxyThreadContext : public ThreadContext void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); } - void setShadowSet(int css){ - return actualTC->setShadowSet(css); - } - uint64_t readPC() { return actualTC->readPC(); } void setPC(uint64_t val) { actualTC->setPC(val); } -- cgit v1.2.3