From 7f1603d20728d7990d1d304bbdb6abdfb7eb53d7 Mon Sep 17 00:00:00 2001 From: Curtis Dunham Date: Fri, 9 May 2014 18:58:46 -0400 Subject: arch: remove inline specifiers on all inst constrs, all ISAs With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions. --- src/arch/alpha/isa/main.isa | 2 +- src/arch/alpha/isa/mem.isa | 2 +- src/arch/arm/isa/templates/basic.isa | 2 +- src/arch/arm/isa/templates/branch.isa | 12 +++++----- src/arch/arm/isa/templates/branch64.isa | 10 ++++---- src/arch/arm/isa/templates/data64.isa | 20 ++++++++-------- src/arch/arm/isa/templates/mem.isa | 24 +++++++++---------- src/arch/arm/isa/templates/mem64.isa | 2 +- src/arch/arm/isa/templates/misc.isa | 36 ++++++++++++++--------------- src/arch/arm/isa/templates/misc64.isa | 4 ++-- src/arch/arm/isa/templates/mult.isa | 4 ++-- src/arch/arm/isa/templates/pred.isa | 6 ++--- src/arch/arm/isa/templates/vfp.isa | 8 +++---- src/arch/arm/isa/templates/vfp64.isa | 10 ++++---- src/arch/mips/isa/formats/basic.isa | 2 +- src/arch/mips/isa/formats/mem.isa | 2 +- src/arch/power/isa/formats/basic.isa | 2 +- src/arch/power/isa/formats/integer.isa | 6 ++--- src/arch/power/isa/formats/mem.isa | 2 +- src/arch/sparc/isa/formats/basic.isa | 4 ++-- src/arch/sparc/isa/formats/mem/blockmem.isa | 4 ++-- src/arch/sparc/isa/formats/priv.isa | 2 +- src/arch/x86/isa/formats/basic.isa | 2 +- src/arch/x86/isa/macroop.isa | 2 +- src/arch/x86/isa/microops/fpop.isa | 2 +- src/arch/x86/isa/microops/ldstop.isa | 2 +- src/arch/x86/isa/microops/limmop.isa | 2 +- src/arch/x86/isa/microops/mediaop.isa | 4 ++-- src/arch/x86/isa/microops/regop.isa | 4 ++-- src/arch/x86/isa/microops/seqop.isa | 4 ++-- src/arch/x86/isa/microops/specop.isa | 6 ++--- 31 files changed, 97 insertions(+), 97 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 4d7dccb15..b2b35a1c1 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -314,7 +314,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index ef140f515..73b04c573 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -155,7 +155,7 @@ def template CompleteAccDeclare {{ }}; def template LoadStoreConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index de4506e05..e202a4768 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -73,7 +73,7 @@ def template BasicConstructor {{ }}; def template BasicConstructor64 {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa index ee06bf573..c8efdb7a6 100644 --- a/src/arch/arm/isa/templates/branch.isa +++ b/src/arch/arm/isa/templates/branch.isa @@ -48,7 +48,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -81,7 +81,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImmCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -110,7 +110,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchRegCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchRegRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) @@ -218,7 +218,7 @@ class %(class_name)s : public %(base_class)s // Only used by CBNZ, CBZ which is conditional based on // a register value even though the instruction is always unconditional. def template BranchImmRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa index 84b3e6ae7..241d12260 100644 --- a/src/arch/arm/isa/templates/branch64.isa +++ b/src/arch/arm/isa/templates/branch64.isa @@ -48,7 +48,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImm64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImmCond64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -89,7 +89,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) @@ -130,7 +130,7 @@ class %(class_name)s : public %(base_class)s }}; def template BranchImmImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa index b6f7ce8d0..7b0438a01 100644 --- a/src/arch/arm/isa/templates/data64.isa +++ b/src/arch/arm/isa/templates/data64.isa @@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXSRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXERegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -124,7 +124,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataX1RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) @@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataX2RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) @@ -168,7 +168,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataX2RegImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -192,7 +192,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataX3RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -216,7 +216,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXCondCompImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, @@ -241,7 +241,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXCondCompRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, @@ -266,7 +266,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataXCondSelConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 7682c277d..e052cbb9d 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -860,7 +860,7 @@ def template CompleteAccDeclare {{ }}; def template RfeConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_base, (AddrMode)_mode, _wb) @@ -889,7 +889,7 @@ def template RfeConstructor {{ }}; def template SrsConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (OperatingMode)_regMode, (AddrMode)_mode, _wb) @@ -912,7 +912,7 @@ def template SrsConstructor {{ }}; def template SwapConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) @@ -927,7 +927,7 @@ def template SwapConstructor {{ }}; def template LoadStoreDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -952,7 +952,7 @@ def template LoadStoreDImmConstructor {{ }}; def template StoreExDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -979,7 +979,7 @@ def template StoreExDImmConstructor {{ }}; def template LoadStoreImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) @@ -1002,7 +1002,7 @@ def template LoadStoreImmConstructor {{ }}; def template StoreExImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1028,7 +1028,7 @@ def template StoreExImmConstructor {{ }}; def template StoreDRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1056,7 +1056,7 @@ def template StoreDRegConstructor {{ }}; def template StoreRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1083,7 +1083,7 @@ def template StoreRegConstructor {{ }}; def template LoadDRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1123,7 +1123,7 @@ def template LoadDRegConstructor {{ }}; def template LoadRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1189,7 +1189,7 @@ def template LoadRegConstructor {{ }}; def template LoadImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index 87dcba988..4d4b27ba9 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -589,7 +589,7 @@ def template LoadStoreImmDU64Constructor {{ }}; def template StoreImmDEx64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 36db5b6c2..c3866a51f 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s }}; def template MrsConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { @@ -78,7 +78,7 @@ class %(class_name)s : public %(base_class)s }}; def template MrsBankedRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _sysM, bool _r) @@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s }}; def template MsrBankedRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t _sysM, bool _r) @@ -137,7 +137,7 @@ class %(class_name)s : public %(base_class)s }}; def template MsrRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) @@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s }}; def template MsrImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) @@ -190,7 +190,7 @@ class %(class_name)s : public %(base_class)s }}; def template MrrcOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex op1, IntRegIndex dest, IntRegIndex dest2, @@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s }}; def template McrrOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex op1, IntRegIndex op2, IntRegIndex dest, @@ -249,7 +249,7 @@ class %(class_name)s : public %(base_class)s }}; def template ImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { %(constructor)s; @@ -273,7 +273,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { @@ -299,7 +299,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { @@ -326,7 +326,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -357,7 +357,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -387,7 +387,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) @@ -417,7 +417,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) @@ -446,7 +446,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegImmImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) @@ -476,7 +476,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegImmImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, @@ -506,7 +506,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegImmRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) @@ -536,7 +536,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegImmRegShiftOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa index 09d3d4470..3ccb3dc17 100644 --- a/src/arch/arm/isa/templates/misc64.isa +++ b/src/arch/arm/isa/templates/misc64.isa @@ -51,7 +51,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegImmImmOp64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, @@ -77,7 +77,7 @@ class %(class_name)s : public %(base_class)s }}; def template RegRegRegImmOp64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa index dd4847fd4..0099e5c9d 100644 --- a/src/arch/arm/isa/templates/mult.isa +++ b/src/arch/arm/isa/templates/mult.isa @@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s }}; def template Mult3Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2) @@ -78,7 +78,7 @@ class %(class_name)s : public %(base_class)s }}; def template Mult4Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2, diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 42f515a3c..9973e9a2a 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -62,7 +62,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, @@ -101,7 +101,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -146,7 +146,7 @@ class %(class_name)s : public %(base_class)s }}; def template DataRegRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index 176b6604c..fbd7275d5 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -166,7 +166,7 @@ class %(class_name)s : public %(base_class)s }}; def template FpRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -193,7 +193,7 @@ class %(class_name)s : public %(base_class)s }}; def template FpRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) @@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s }}; def template FpRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, @@ -250,7 +250,7 @@ class %(class_name)s : public %(base_class)s }}; def template FpRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa index 0935cd78a..761a853a9 100644 --- a/src/arch/arm/isa/templates/vfp64.isa +++ b/src/arch/arm/isa/templates/vfp64.isa @@ -38,7 +38,7 @@ // Authors: Thomas Grocutt def template AA64FpRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -52,7 +52,7 @@ def template AA64FpRegRegOpConstructor {{ }}; def template AA64FpRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) @@ -65,7 +65,7 @@ def template AA64FpRegImmOpConstructor {{ }}; def template AA64FpRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, @@ -81,7 +81,7 @@ def template AA64FpRegRegImmOpConstructor {{ }}; def template AA64FpRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s }}; def template AA64FpRegRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa index 92568c5fa..46c48548c 100644 --- a/src/arch/mips/isa/formats/basic.isa +++ b/src/arch/mips/isa/formats/basic.isa @@ -52,7 +52,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 64d000005..3e7a8de5a 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -166,7 +166,7 @@ def template CompleteAccDeclare {{ }}; def template LoadStoreConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff --git a/src/arch/power/isa/formats/basic.isa b/src/arch/power/isa/formats/basic.isa index adb5e7ef8..c6532429c 100644 --- a/src/arch/power/isa/formats/basic.isa +++ b/src/arch/power/isa/formats/basic.isa @@ -49,7 +49,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa index 0766826ec..4489dae47 100644 --- a/src/arch/power/isa/formats/integer.isa +++ b/src/arch/power/isa/formats/integer.isa @@ -36,7 +36,7 @@ // Instruction class constructor template when Rc is set. def template IntRcConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; rcSet = true; @@ -46,7 +46,7 @@ def template IntRcConstructor {{ // Instruction class constructor template when OE is set. def template IntOeConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; oeSet = true; @@ -56,7 +56,7 @@ def template IntOeConstructor {{ // Instruction class constructor template when both Rc and OE are set. def template IntRcOeConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; rcSet = true; diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index a409eefac..22a102ad7 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -64,7 +64,7 @@ def template CompleteAccDeclare {{ def template LoadStoreConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 915e34564..feb99e140 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -93,7 +93,7 @@ def template BasicDeclareWithMnemonic {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; @@ -102,7 +102,7 @@ def template BasicConstructor {{ // Basic instruction class constructor template. def template BasicConstructorWithMnemonic {{ - inline %(class_name)s::%(class_name)s(const char * mnemonic, + %(class_name)s::%(class_name)s(const char * mnemonic, ExtMachInst machInst) : %(base_class)s(mnemonic, machInst, %(op_class)s) { diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index c397d2675..03b395b12 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -240,7 +240,7 @@ def template BlockMemDeclare {{ // Basic instruction class constructor template. def template BlockMemConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; @@ -256,7 +256,7 @@ def template BlockMemConstructor {{ }}; def template BlockMemMicroConstructor {{ - inline %(class_name)s:: + %(class_name)s:: %(class_name)s_%(micro_pc)s:: %(class_name)s_%(micro_pc)s(ExtMachInst machInst) : %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]", diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index e3242aab8..c12a31b10 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -186,7 +186,7 @@ output decoder {{ }}; def template ControlRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, "%(reg_name)s") { diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa index 6624c03ae..d8f8592d7 100644 --- a/src/arch/x86/isa/formats/basic.isa +++ b/src/arch/x86/isa/formats/basic.isa @@ -68,7 +68,7 @@ def template BasicDeclare {{ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index d510a0c7c..818cfc3ea 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -110,7 +110,7 @@ def template MacroDisassembly {{ // Basic instruction class constructor template. def template MacroConstructor {{ - inline X86Macroop::%(class_name)s::%(class_name)s( + X86Macroop::%(class_name)s::%(class_name)s( ExtMachInst machInst, EmulEnv _env) : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s, _env) { diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 3c6753712..131284076 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -88,7 +88,7 @@ def template MicroFpOpDeclare {{ }}; def template MicroFpOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm) : diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 1b22b88de..b82cf57e0 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -254,7 +254,7 @@ def template MicroLdStOpDeclare {{ }}; def template MicroLdStOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, uint8_t _scale, InstRegIndex _index, InstRegIndex _base, uint64_t _disp, InstRegIndex _segment, diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 2c61aaa45..e7cd548ec 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -90,7 +90,7 @@ def template MicroLimmOpDisassembly {{ }}; def template MicroLimmOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 0f41491f9..fecdab863 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -74,7 +74,7 @@ def template MediaOpImmDeclare {{ }}; def template MediaOpRegConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : @@ -87,7 +87,7 @@ def template MediaOpRegConstructor {{ }}; def template MediaOpImmConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index d77e5f559..b957a164a 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -130,7 +130,7 @@ def template MicroRegOpImmDeclare {{ }}; def template MicroRegOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : @@ -144,7 +144,7 @@ def template MicroRegOpConstructor {{ }}; def template MicroRegOpImmConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext) : diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index d60ddced7..72c28b1fe 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -84,7 +84,7 @@ def template SeqOpExecute {{ }}; output decoder {{ - inline SeqOpBase::SeqOpBase( + SeqOpBase::SeqOpBase( ExtMachInst machInst, const char * mnemonic, const char * instMnem, uint64_t setFlags, uint16_t _target, uint8_t _cc) : X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass), @@ -94,7 +94,7 @@ output decoder {{ }}; def template SeqOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, uint16_t _target, uint8_t _cc) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 2f6bbd58d..a13250589 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -112,7 +112,7 @@ output exec {{ }}; output decoder {{ - inline MicroFaultBase::MicroFaultBase( + MicroFaultBase::MicroFaultBase( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, Fault _fault, uint8_t _cc) : X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass), @@ -122,7 +122,7 @@ output decoder {{ }}; def template MicroFaultConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, Fault _fault, uint8_t _cc) : %(base_class)s(machInst, instMnem, setFlags, _fault, _cc) @@ -219,7 +219,7 @@ def template MicroFenceOpDeclare {{ }}; def template MicroFenceOpConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, %(op_class)s) -- cgit v1.2.3