From 812e390693253818c49585daf35692759a1c82d4 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 14 Nov 2009 19:22:29 -0800
Subject: ARM: Fix up the implmentation of the mrs instruction.

---
 src/arch/arm/isa/decoder.isa | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 20b544a7c..cd13fa420 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -110,7 +110,9 @@ format DataOp {
             }
             1: decode MISC_OPCODE {
                 0x0: decode OPCODE {
-                    0x8: PredOp::mrs_cpsr({{ Rd = Cpsr | CondCodes; }});
+                    0x8: PredOp::mrs_cpsr({{
+                        Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
+                    }});
                     0x9: PredOp::msr_cpsr({{
                         //assert(!RN<1:0>);
                         if (OPCODE_18) {
@@ -120,7 +122,7 @@ format DataOp {
                             CondCodes = mbits(Rm, 31,27);
                         }
                     }});
-                    0xa: PredOp::mrs_spsr({{ Rd = 0; // should be SPSR}});
+                    0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
                     0xb: WarnUnimpl::msr_spsr();
                 }
                 0x1: decode OPCODE {
-- 
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