From 13ac9a419dcf2e1e0335bc65b20837e538a9beee Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 18:52:20 -0400
Subject: One step closet to having NACK's work.
src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
---
src/cpu/memtest/memtest.cc | 7 ++++---
src/cpu/memtest/memtest.hh | 2 +-
src/mem/cache/base_cache.cc | 5 ++++-
src/mem/cache/cache_impl.hh | 10 ++++++++--
4 files changed, 17 insertions(+), 7 deletions(-)
(limited to 'src')
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 609a07a8e..127cad414 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -71,7 +71,8 @@ MemTest::CpuPort::recvAtomic(Packet *pkt)
void
MemTest::CpuPort::recvFunctional(Packet *pkt)
{
- memtest->completeRequest(pkt);
+ //Do nothing if we see one come through
+ return;
}
void
@@ -325,7 +326,7 @@ MemTest::tick()
} else {
paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
}
- // bool probe = (random() % 2 == 1) && !req->isUncacheable();
+ //bool probe = (random() % 2 == 1) && !req->isUncacheable();
bool probe = false;
paddr &= ~((1 << access_size) - 1);
@@ -364,7 +365,7 @@ MemTest::tick()
if (probe) {
cachePort.sendFunctional(pkt);
-// completeRequest(pkt, result);
+ completeRequest(pkt);
} else {
// req->completionEvent = new MemCompleteEvent(req, result, this);
if (!cachePort.sendTiming(pkt)) {
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 278012eba..87ecc6de3 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -113,7 +113,7 @@ class MemTest : public MemObject
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
};
CpuPort cachePort;
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 1a0f63d17..8e2f4d233 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -217,7 +217,10 @@ BaseCache::CacheEvent::process()
}
//Response
//Know the packet to send
- pkt->result = Packet::Success;
+ if (pkt->flags & NACKED_LINE)
+ pkt->result = Packet::Nacked;
+ else
+ pkt->result = Packet::Success;
pkt->makeTimingResponse();
if (!cachePort->drainList.empty()) {
//Already blocked waiting for bus, just append
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index bde7ac04b..af12b9255 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -306,6 +306,13 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
{
BlkType *blk = NULL;
if (pkt->senderState) {
+ if (pkt->result == Packet::Nacked) {
+ pkt->reinitFromRequest();
+ panic("Unimplemented NACK of packet\n");
+ }
+ if (pkt->result == Packet::BadAddress) {
+ //Make the response a Bad address and send it
+ }
// MemDebug::cacheResponse(pkt);
DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->getAddr(),
pkt->getAddr() & (((ULL(1))<<48)-1));
@@ -392,7 +399,6 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
assert(!(pkt->flags & SATISFIED));
pkt->flags |= SATISFIED;
pkt->flags |= NACKED_LINE;
- assert("Don't detect these on the other side yet\n");
respondToSnoop(pkt, curTick + hitLatency);
return;
}
@@ -406,7 +412,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
//@todo Make it so that a read to a pending read can't be exclusive now.
//Set the address so find match works
- assert("Don't have invalidates yet\n");
+ panic("Don't have invalidates yet\n");
invalidatePkt->addrOverride(pkt->getAddr());
//Append the invalidate on
--
cgit v1.2.3
From e03b9c9939d7782198c023b23ed33cde131f48c5 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 19:15:24 -0400
Subject: Fix how upgrades work. Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
---
src/mem/cache/cache_impl.hh | 8 +++-----
src/mem/cache/coherence/coherence_protocol.cc | 2 +-
src/mem/packet.hh | 3 +--
3 files changed, 5 insertions(+), 8 deletions(-)
(limited to 'src')
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index af12b9255..c3c1c0881 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -63,9 +63,8 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
if (pkt->isWrite() && (pkt->req->isLocked())) {
pkt->req->setScResult(1);
}
- if (!(pkt->flags & SATISFIED)) {
- access(pkt);
- }
+ access(pkt);
+
}
else
{
@@ -204,9 +203,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
pkt->getAddr() & (((ULL(1))<<48)-1),
pkt->getAddr() & ~((Addr)blkSize - 1));
- //@todo Should this return latency have the hit latency in it?
-// respond(pkt,curTick+lat);
pkt->flags |= SATISFIED;
+ //Invalidates/Upgrades need no response if they get the bus
// return MA_HIT; //@todo, return values
return true;
}
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index bcf3ce9c5..e28dda3dc 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -271,7 +271,7 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
}
Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq;
- Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeResp : Packet::ReadExResp;
+ Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp;
//@todo add in hardware prefetch to this list
if (protocol == "msi") {
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index be9bf5f57..9d37fe157 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -194,8 +194,7 @@ class Packet
HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
InvalidateReq = IsInvalidate | IsRequest,
WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
- UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
- UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
+ UpgradeReq = IsInvalidate | IsRequest
ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
};
--
cgit v1.2.3
From 9356bcda7b50ae8916eee2dfbad84ed3ea873c1e Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 9 Oct 2006 19:20:28 -0400
Subject: Fix a typo preventing compilation
--HG--
extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
---
src/mem/packet.hh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'src')
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 9d37fe157..56c4caffe 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -194,7 +194,7 @@ class Packet
HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
InvalidateReq = IsInvalidate | IsRequest,
WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
- UpgradeReq = IsInvalidate | IsRequest
+ UpgradeReq = IsInvalidate | IsRequest,
ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
};
--
cgit v1.2.3