From 8549ee4a6dfc86a941cee0a478c01f6f2c146c3c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 29 Oct 2019 15:12:10 -0700 Subject: arch,cpu: Move endianness conversion of inst bytes into the ISA. It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- src/arch/alpha/decoder.hh | 2 +- src/arch/arm/decoder.cc | 2 +- src/arch/mips/decoder.hh | 2 +- src/arch/power/decoder.hh | 2 +- src/arch/riscv/decoder.cc | 1 + src/arch/sparc/decoder.hh | 2 +- src/arch/x86/decoder.hh | 2 +- src/cpu/checker/cpu_impl.hh | 1 - src/cpu/minor/fetch2.cc | 6 ++---- src/cpu/o3/fetch_impl.hh | 3 +-- src/cpu/simple/base.cc | 2 -- 11 files changed, 10 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh index 522359c28..0ee425077 100644 --- a/src/arch/alpha/decoder.hh +++ b/src/arch/alpha/decoder.hh @@ -66,7 +66,7 @@ class Decoder void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - ext_inst = inst; + ext_inst = letoh(inst); instDone = true; if (FullSystem) ext_inst |= (static_cast(pc.pc() & 0x1) << 32); diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc index 4c86ee2c6..a2c504334 100644 --- a/src/arch/arm/decoder.cc +++ b/src/arch/arm/decoder.cc @@ -154,7 +154,7 @@ Decoder::consumeBytes(int numBytes) void Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - data = inst; + data = letoh(inst); offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC; emi.thumb = pc.thumb(); emi.aarch64 = pc.aarch64(); diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh index 4a2fc46a5..825ab8ada 100644 --- a/src/arch/mips/decoder.hh +++ b/src/arch/mips/decoder.hh @@ -68,7 +68,7 @@ class Decoder void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - emi = inst; + emi = letoh(inst); instDone = true; } diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh index cc086adc5..56273f8db 100644 --- a/src/arch/power/decoder.hh +++ b/src/arch/power/decoder.hh @@ -67,7 +67,7 @@ class Decoder void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - emi = inst; + emi = betoh(inst); instDone = true; } diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index 41a52020e..69c392194 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -52,6 +52,7 @@ void Decoder::reset() void Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { + inst = letoh(inst); DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst, fetchPC); diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh index 6fa506f37..8124a6963 100644 --- a/src/arch/sparc/decoder.hh +++ b/src/arch/sparc/decoder.hh @@ -65,7 +65,7 @@ class Decoder void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - emi = inst; + emi = betoh(inst); // The I bit, bit 13, is used to figure out where the ASI // should come from. Use that in the ExtMachInst. This is // slightly redundant, but it removes the need to put a condition diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh index 412b7c73f..064fd3a80 100644 --- a/src/arch/x86/decoder.hh +++ b/src/arch/x86/decoder.hh @@ -310,7 +310,7 @@ class Decoder DPRINTF(Decoder, "Getting more bytes.\n"); basePC = fetchPC; offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC; - fetchChunk = data; + fetchChunk = letoh(data); outOfBytes = false; process(); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 9e4bdcd52..fce4a9fc3 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -285,7 +285,6 @@ Checker::verify(const DynInstPtr &completed_inst) pkt->dataStatic(&machInst); icachePort->sendFunctional(pkt); - machInst = gtoh(machInst); delete pkt; } diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc index d60a1bab0..f047d6816 100644 --- a/src/cpu/minor/fetch2.cc +++ b/src/cpu/minor/fetch2.cc @@ -376,12 +376,10 @@ Fetch2::evaluate() } else { uint8_t *line = line_in->line; - TheISA::MachInst inst_word; /* The instruction is wholly in the line, can just * assign */ - inst_word = TheISA::gtoh( - *(reinterpret_cast - (line + fetch_info.inputIndex))); + auto inst_word = *reinterpret_cast + (line + fetch_info.inputIndex); if (!decoder->instReady()) { decoder->moreBytes(fetch_info.pc, diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 60542b824..47b1ad0c5 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1285,8 +1285,7 @@ DefaultFetch::fetch(bool &status_change) break; } - MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); - decoder[tid]->moreBytes(thisPC, fetchAddr, inst); + decoder[tid]->moreBytes(thisPC, fetchAddr, cacheInsts[blkOffset]); if (decoder[tid]->needMoreBytes()) { blkOffset++; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 3000fae53..566533c73 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -503,8 +503,6 @@ BaseSimpleCPU::preExecute() thread->comInstEventQueue.serviceEvents(t_info.numInst); // decode the instruction - inst = gtoh(inst); - TheISA::PCState pcState = thread->pcState(); if (isRomMicroPC(pcState.microPC())) { -- cgit v1.2.3