From 0b0d5a282a25a936d4aa92ec81ef2bd50141ce03 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:33:44 -0500 Subject: Draining fixes. src/cpu/o3/cpu.cc: Handle draining properly when CPU isn't actually being used. src/cpu/simple/atomic.cc: Be sure to set status properly when draining. src/mem/bus.cc: Fix for draining. --HG-- extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f --- src/cpu/o3/cpu.cc | 6 ++++++ src/cpu/simple/atomic.cc | 3 +++ src/mem/bus.cc | 5 ++++- 3 files changed, 13 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index dfe42d882..580816372 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -819,6 +819,12 @@ unsigned int FullO3CPU::drain(Event *drain_event) { DPRINTF(O3CPU, "Switching out\n"); + + // If the CPU isn't doing anything, then return immediately. + if (_status == Idle || _status == SwitchedOut) { + return 0; + } + drainCount = 0; fetch.drain(); decode.drain(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4f68cfd6f..f94ea0917 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -213,6 +213,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) break; } } + if (_status != Running) { + _status = Idle; + } } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 7b65d252b..ae87d8099 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -242,8 +242,11 @@ Bus::recvRetry(int id) } } //If we weren't able to drain before, we might be able to now. - if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) + if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) { drainEvent->process(); + // Clear the drain event once we're done with it. + drainEvent = NULL; + } } Port * -- cgit v1.2.3 From 21f43bfc4b01051e688a4eec4ce5aef12ad2c951 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 9 Nov 2006 11:37:26 -0500 Subject: Be sure to populate the packet's finishTime field in the atomic timing case. --HG-- extra : convert_revision : ef34818eb2dea5b3a8e754bf56745a7cd2497bf0 --- src/mem/bus.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/mem/bus.cc b/src/mem/bus.cc index ae87d8099..8ea67a0e4 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -370,6 +370,10 @@ Bus::recvAtomic(PacketPtr pkt) DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); + + // Assume one bus cycle in order to get through. This may have + // some clock skew issues yet again... + pkt->finishTime = curTick + clock; Tick snoopTime = atomicSnoop(pkt); if (snoopTime) return snoopTime; //Snoop satisfies it -- cgit v1.2.3 From 12e26c68c3e12a17c29b694012819bc7bae7bb5a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 20:15:30 -0500 Subject: Updates to support new interrupt processing and removal of PcPAL. src/arch/alpha/interrupts.hh: No need for this now that the ThreadContext is being used to set these IPRs in interrupts. Also split up the interrupt checking from the updating of the IPL and interrupt summary. src/arch/alpha/tlb.cc: Check the PC for whether or not it's in PAL mode, not the addr. src/cpu/o3/alpha/cpu.hh: Split up getting the interrupt from actually processing the interrupt. src/cpu/o3/alpha/cpu_impl.hh: Splut up the processing of interrupts. src/cpu/o3/commit_impl.hh: Update for ISA-oriented interrupt changes. src/cpu/o3/fetch_impl.hh: Fix broken if statement from PcPAL updates, and properly populate the request fields. Also more debugging output. src/cpu/ozone/cpu_impl.hh: Updates for ISA-oriented interrupt stuff. src/cpu/ozone/front_end_impl.hh: Populate request fields properly. src/cpu/simple/base.cc: Update for interrupt stuff. --HG-- extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c --- src/arch/alpha/interrupts.hh | 28 +++++++++++++---------- src/arch/alpha/tlb.cc | 2 +- src/cpu/o3/alpha/cpu.hh | 7 ++++-- src/cpu/o3/alpha/cpu_impl.hh | 22 +++++++++++------- src/cpu/o3/commit_impl.hh | 30 ++++++++++++++++--------- src/cpu/o3/fetch_impl.hh | 25 ++++++++++++++++----- src/cpu/ozone/cpu_impl.hh | 50 +++++------------------------------------ src/cpu/ozone/front_end_impl.hh | 4 ++-- src/cpu/simple/base.cc | 1 + 9 files changed, 82 insertions(+), 87 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index 75031ae47..a86fb2d7b 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -49,6 +49,7 @@ namespace AlphaISA { memset(interrupts, 0, sizeof(interrupts)); intstatus = 0; + newInfoSet = false; } void post(int int_num, int index) @@ -137,18 +138,10 @@ namespace AlphaISA } if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { - tc->setMiscReg(IPR_ISR, summary); - tc->setMiscReg(IPR_INTID, ipl); - - /* The following needs to be added back in somehow */ - // Checker needs to know these two registers were updated. -/*#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif*/ - +// assert(!newInfoSet); + newIpl = ipl; + newSummary = newSummary; + newInfoSet = true; DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", tc->readMiscReg(IPR_IPLR), ipl, summary); @@ -158,7 +151,18 @@ namespace AlphaISA } } + void updateIntrInfo(ThreadContext *tc) + { + assert(newInfoSet); + tc->setMiscReg(IPR_ISR, newSummary); + tc->setMiscReg(IPR_INTID, newIpl); + newInfoSet = false; + } + private: + bool newInfoSet; + int newIpl; + int newSummary; }; } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index ae302e686..af69e45c0 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,7 +292,7 @@ namespace AlphaISA Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { - if (PcPAL(req->getVaddr())) { + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); hits++; diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index b62550062..0078db69f 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -156,8 +156,11 @@ class AlphaO3CPU : public FullO3CPU bool simPalCheck(int palFunc, unsigned tid); - /** Processes any interrupts. */ - void processInterrupts(); + /** Returns the Fault for any valid interrupt. */ + Fault getInterrupts(); + + /** Processes any an interrupt fault. */ + void processInterrupts(Fault interrupt); /** Halts the CPU. */ void halt() { panic("Halt not implemented!\n"); } diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 04eadfa5a..f5c394826 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -266,9 +266,17 @@ AlphaO3CPU::simPalCheck(int palFunc, unsigned tid) return true; } +template +Fault +AlphaO3CPU::getInterrupts() +{ + // Check if there are any outstanding interrupts + return this->interrupts.getInterrupt(this->threadContexts[0]); +} + template void -AlphaO3CPU::processInterrupts() +AlphaO3CPU::processInterrupts(Fault interrupt) { // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 @@ -276,14 +284,12 @@ AlphaO3CPU::processInterrupts() // @todo: Possibly consolidate the interrupt checking code. // @todo: Allow other threads to handle interrupts. - // Check if there are any outstanding interrupts - //Handle the interrupts - Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); + assert(interrupt != NoFault); + this->interrupts.updateIntrInfo(this->threadContexts[0]); - if (interrupt != NoFault) { - this->checkInterrupts = false; - this->trap(interrupt, 0); - } + DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); + this->checkInterrupts = false; + this->trap(interrupt, 0); } #endif // FULL_SYSTEM diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 30052a148..d8e079a7e 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -640,8 +640,18 @@ DefaultCommit::commit() // @todo: Allow other threads to handle interrupts. if (cpu->checkInterrupts && cpu->check_interrupts(cpu->tcBase(0)) && + commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { + + // Get any interrupt that happened + Fault intr = cpu->getInterrupts(); + + // Exit this if block if there's no fault. + if (intr == NoFault) { + goto commit_insts; + } + // Tell fetch that there is an interrupt pending. This will // make fetch wait until it sees a non PAL-mode PC, at which // point it stops fetching instructions. @@ -650,26 +660,24 @@ DefaultCommit::commit() // Wait until the ROB is empty and all stores have drained in // order to enter the interrupt. if (rob->isEmpty() && !iewStage->hasStoresToWB()) { - // Not sure which thread should be the one to interrupt. For now - // always do thread 0. + // Squash or record that I need to squash this cycle if + // an interrupt needed to be handled. + DPRINTF(Commit, "Interrupt detected.\n"); + assert(!thread[0]->inSyscall); thread[0]->inSyscall = true; - // CPU will handle implementation of the interrupt. - cpu->processInterrupts(); + // CPU will handle interrupt. + cpu->processInterrupts(intr); - // Now squash or record that I need to squash this cycle. - commitStatus[0] = TrapPending; - - // Exit state update mode to avoid accidental updating. thread[0]->inSyscall = false; + commitStatus[0] = TrapPending; + // Generate trap squash event. generateTrapEvent(0); toIEW->commitInfo[0].clearInterrupt = true; - - DPRINTF(Commit, "Interrupt detected.\n"); } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } @@ -679,7 +687,7 @@ DefaultCommit::commit() //////////////////////////////////// // Check for any possible squashes, handle them first //////////////////////////////////// - + commit_insts: std::list::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 5ef6e27ea..b1fae8cf0 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -559,27 +559,36 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid Fault fault = NoFault; //AlphaDep - if (cacheBlocked || isSwitchedOut() || - (interruptPending && (fetch_PC & 0x3))) { + if (cacheBlocked) { + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n", + tid); + return false; + } else if (isSwitchedOut()) { + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n", + tid); + return false; + } else if (interruptPending && !(fetch_PC & 0x3)) { // Hold off fetch from getting new instructions when: // Cache is blocked, or // while an interrupt is pending and we're not in PAL mode, or // fetch is switched out. + DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n", + tid); return false; } // Align the fetch PC so it's at the start of a cache block. - fetch_PC = icacheBlockAlignPC(fetch_PC); + Addr block_PC = icacheBlockAlignPC(fetch_PC); // If we've already got the block, no need to try to fetch it again. - if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) { + if (cacheDataValid[tid] && block_PC == cacheDataPC[tid]) { return true; } // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0, + RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, fetch_PC, cpu->readCpuId(), tid); memReq[tid] = mem_req; @@ -609,7 +618,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid Packet::ReadReq, Packet::Broadcast); data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]); - cacheDataPC[tid] = fetch_PC; + cacheDataPC[tid] = block_PC; cacheDataValid[tid] = false; DPRINTF(Fetch, "Fetch: Doing instruction read.\n"); @@ -1050,12 +1059,16 @@ DefaultFetch::fetch(bool &status_change) } else { if (fetchStatus[tid] == Idle) { ++fetchIdleCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid); } else if (fetchStatus[tid] == Blocked) { ++fetchBlockedCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid); } else if (fetchStatus[tid] == Squashing) { ++fetchSquashCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid); } else if (fetchStatus[tid] == IcacheWaitResponse) { ++icacheStallCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n", tid); } // Status is Idle, Squashing, Blocked, or IcacheWaitResponse, so diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 86c973a0f..accc8d294 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -700,52 +700,12 @@ OzoneCPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - int ipl = 0; - int summary = 0; + Fault interrupt = this->interrupts.getInterrupt(thread.getTC()); - checkInterrupts = false; - - if (thread.readMiscReg(IPR_ASTRR)) - panic("asynchronous traps not implemented\n"); - - if (thread.readMiscReg(IPR_SIRR)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (thread.readMiscReg(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = intr_status(); - - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) { - thread.setMiscReg(IPR_ISR, summary); - thread.setMiscReg(IPR_INTID, ipl); -#if USE_CHECKER - // @todo: Make this more transparent - if (checker) { - checker->threadBase()->setMiscReg(IPR_ISR, summary); - checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif - Fault fault = new InterruptFault; - fault->invoke(thread.getTC()); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - thread.readMiscReg(IPR_IPLR), ipl, summary); + if (interrupt != NoFault) { + this->interrupts.updateIntrInfo(thread.getTC()); + this->checkInterrupts = false; + interrupt->invoke(thread.getTC()); } } diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 73ca6afbe..198ce0308 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -476,8 +476,8 @@ FrontEnd::fetchCacheLine() // Setup the memReq to do a read of the first isntruction's address. // Set the appropriate read size and flags as well. - memReq = new Request(0, fetch_PC, cacheBlkSize, flags, - fetch_PC, cpu->readCpuId(), 0); + memReq = new Request(0, fetch_PC, cacheBlkSize, 0, + PC, cpu->readCpuId(), 0); // Translate the instruction request. fault = cpu->translateInstReq(memReq, thread); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ab438aa77..4e5754bbb 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -315,6 +315,7 @@ BaseSimpleCPU::checkForInterrupts() Fault interrupt = interrupts.getInterrupt(tc); if (interrupt != NoFault) { + interrupts.updateIntrInfo(tc); checkInterrupts = false; interrupt->invoke(tc); } -- cgit v1.2.3 From 437436a2f706477439cfb81d254e8f7b454450a5 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 21:49:51 -0500 Subject: Fix for non-FS compile. --HG-- extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a --- src/cpu/o3/commit_impl.hh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index d8e079a7e..b394759b9 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -682,12 +682,15 @@ DefaultCommit::commit() DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } } + + // Label for goto. Not pretty but more readable than really big + // if statement above. + commit_insts: #endif // FULL_SYSTEM //////////////////////////////////// // Check for any possible squashes, handle them first //////////////////////////////////// - commit_insts: std::list::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { -- cgit v1.2.3 From 8a0cbbe27b851fac4d3288e56878f59e5c207c0e Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 23:30:09 -0500 Subject: Fix for regression failure. src/cpu/o3/fetch_impl.hh: Fetch needs to make sure it isn't waiting on an Icache access. --HG-- extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1 --- src/cpu/o3/fetch_impl.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a5478d4f8..25faa407e 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -985,7 +985,9 @@ DefaultFetch::checkSignalsAndUpdate(unsigned tid) } } - if (checkStall(tid) && fetchStatus[tid] != IcacheWaitResponse) { + if (checkStall(tid) && + fetchStatus[tid] != IcacheWaitResponse && + fetchStatus[tid] != IcacheWaitRetry) { DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid); fetchStatus[tid] = Blocked; -- cgit v1.2.3 From 9e53eed88a2cb33247c2bab747846e2c23df8d68 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 12 Nov 2006 23:31:29 -0500 Subject: Fix typo. --HG-- extra : convert_revision : 05db10e20d33302fe830d5759b8881b1233aca87 --- src/cpu/ozone/cpu_builder.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 155f0ce09..e7ecfc496 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -67,7 +67,7 @@ Param profile; Param do_quiesce; Param do_checkpoint_insts; -Param do_statistics_insts +Param do_statistics_insts; #else SimObjectVectorParam workload; //SimObjectParam page_table; -- cgit v1.2.3 From 4c21fab575b146c0e9d374c352124c4d626fec00 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 13 Nov 2006 00:26:38 -0500 Subject: Change warn to DPRINTF. --HG-- extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354 --- src/cpu/o3/lsq_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 317e23b14..5e7945c1c 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -46,7 +46,7 @@ template void LSQ::DcachePort::recvFunctional(PacketPtr pkt) { - warn("O3CPU doesn't update things on a recvFunctional."); + DPRINTF(LSQ, "LSQ doesn't update things on a recvFunctional."); } template -- cgit v1.2.3 From 0f633c5fee2a371bc216ca71192c6ff02dcc3b5c Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 12 Nov 2006 22:03:42 -0800 Subject: Make setRegWithEffect do something in SE mode. --HG-- extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8 --- src/arch/alpha/miscregfile.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 4cf57a690..962d4609f 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -132,7 +132,6 @@ namespace AlphaISA MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, ThreadContext *tc) { -#if FULL_SYSTEM switch(misc_reg) { case MISCREG_FPCR: fpcr = val; @@ -150,12 +149,13 @@ namespace AlphaISA intr_flag = val; return; default: - return setIpr(misc_reg, val, tc); - } +#if FULL_SYSTEM + setIpr(misc_reg, val, tc); #else - //panic("No registers with side effects in SE mode!"); - return; + panic("No registers with side effects in SE mode!"); #endif + return; + } } } -- cgit v1.2.3 From 41a9196f60a0399a0ef1e4cfe8e77391886120cf Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 13 Nov 2006 02:49:03 -0500 Subject: More interrupt reworking. --HG-- extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4 --- src/cpu/o3/commit.hh | 3 +++ src/cpu/o3/commit_impl.hh | 52 +++++++++++++++++++++++------------------------ 2 files changed, 29 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 7575783f7..0d7d82529 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -392,6 +392,9 @@ class DefaultCommit */ Tick trapLatency; + /** The interrupt fault. */ + Fault interrupt; + /** The commit PC of each thread. Refers to the instruction that * is currently being processed/committed. */ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index b394759b9..e72679710 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -122,6 +122,9 @@ DefaultCommit::DefaultCommit(Params *params) tcSquash[i] = false; PC[i] = nextPC[i] = nextNPC[i] = 0; } +#if FULL_SYSTEM + interrupt = NoFault; +#endif } template @@ -635,28 +638,7 @@ DefaultCommit::commit() ////////////////////////////////////// #if FULL_SYSTEM - // Process interrupts if interrupts are enabled, not in PAL mode, - // and no other traps or external squashes are currently pending. - // @todo: Allow other threads to handle interrupts. - if (cpu->checkInterrupts && - cpu->check_interrupts(cpu->tcBase(0)) && - commitStatus[0] != TrapPending && - !trapSquash[0] && - !tcSquash[0]) { - - // Get any interrupt that happened - Fault intr = cpu->getInterrupts(); - - // Exit this if block if there's no fault. - if (intr == NoFault) { - goto commit_insts; - } - - // Tell fetch that there is an interrupt pending. This will - // make fetch wait until it sees a non PAL-mode PC, at which - // point it stops fetching instructions. - toIEW->commitInfo[0].interruptPending = true; - + if (interrupt != NoFault) { // Wait until the ROB is empty and all stores have drained in // order to enter the interrupt. if (rob->isEmpty() && !iewStage->hasStoresToWB()) { @@ -668,7 +650,7 @@ DefaultCommit::commit() thread[0]->inSyscall = true; // CPU will handle interrupt. - cpu->processInterrupts(intr); + cpu->processInterrupts(interrupt); thread[0]->inSyscall = false; @@ -677,15 +659,33 @@ DefaultCommit::commit() // Generate trap squash event. generateTrapEvent(0); + // Clear the interrupt now that it's been handled toIEW->commitInfo[0].clearInterrupt = true; + interrupt = NoFault; } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } + } else if (cpu->checkInterrupts && + cpu->check_interrupts(cpu->tcBase(0)) && + commitStatus[0] != TrapPending && + !trapSquash[0] && + !tcSquash[0]) { + // Process interrupts if interrupts are enabled, not in PAL + // mode, and no other traps or external squashes are currently + // pending. + // @todo: Allow other threads to handle interrupts. + + // Get any interrupt that happened + interrupt = cpu->getInterrupts(); + + if (interrupt != NoFault) { + // Tell fetch that there is an interrupt pending. This + // will make fetch wait until it sees a non PAL-mode PC, + // at which point it stops fetching instructions. + toIEW->commitInfo[0].interruptPending = true; + } } - // Label for goto. Not pretty but more readable than really big - // if statement above. - commit_insts: #endif // FULL_SYSTEM //////////////////////////////////// -- cgit v1.2.3 From afed455e777348596db9ff9786d6dae03a956c89 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 13 Nov 2006 12:20:08 -0800 Subject: Expose debugBreakCycle through swig and get rid of the Debug param context --HG-- extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4 --- src/SConscript | 1 + src/python/SConscript | 6 ++++++ src/python/m5/main.py | 3 ++- src/python/m5/objects/Root.py | 2 -- src/python/swig/debug.i | 19 +++++++++++++++++++ src/sim/debug.cc | 36 ++++-------------------------------- src/sim/main.cc | 4 +++- 7 files changed, 35 insertions(+), 36 deletions(-) create mode 100644 src/python/swig/debug.i (limited to 'src') diff --git a/src/SConscript b/src/SConscript index 385047f7f..9d54174ab 100644 --- a/src/SConscript +++ b/src/SConscript @@ -129,6 +129,7 @@ base_sources = Split(''' mem/cache/cache_builder.cc + python/swig/debug_wrap.cc python/swig/main_wrap.cc sim/builder.cc diff --git a/src/python/SConscript b/src/python/SConscript index 5c351c32a..be6248bab 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -98,11 +98,17 @@ pyzip_files.append('m5/defines.py') pyzip_files.append('m5/info.py') pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) +env.Command(['swig/debug_wrap.cc', 'm5/internal/debug.py'], + 'swig/debug.i', + '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' + '-o ${TARGETS[0]} $SOURCES') + env.Command(['swig/main_wrap.cc', 'm5/internal/main.py'], 'swig/main.i', '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES') +pyzip_dep_files.append('m5/internal/debug.py') pyzip_dep_files.append('m5/internal/main.py') # Action function to build the zip archive. Uses the PyZipFile module diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 1e224c0cf..114c668a6 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -275,7 +275,8 @@ def main(): objects.Statistics.text_file = options.stats_file # set debugging options - objects.Debug.break_cycles = options.debug_break + for when in options.debug_break: + internal.debug.schedBreakCycle(int(when)) # set tracing options objects.Trace.flags = options.trace_flags diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index 8e8d87f6d..b6123f192 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -5,7 +5,6 @@ from Serialize import Statreset from Statistics import Statistics from Trace import Trace from ExeTrace import ExecutionTrace -from Debug import Debug class Root(SimObject): type = 'Root' @@ -22,4 +21,3 @@ class Root(SimObject): trace = Trace() exetrace = ExecutionTrace() serialize = Serialize() - debug = Debug() diff --git a/src/python/swig/debug.i b/src/python/swig/debug.i new file mode 100644 index 000000000..8da2974ca --- /dev/null +++ b/src/python/swig/debug.i @@ -0,0 +1,19 @@ +%module debug + +%{ +// include these files when compiling debug_wrap.cc +#include "sim/host.hh" +%} + +%include "stdint.i" +%include "sim/host.hh" + +%inline %{ +extern void schedBreakCycle(Tick when); +%} + +%wrapper %{ +// fix up module name to reflect the fact that it's inside the m5 package +#undef SWIG_name +#define SWIG_name "m5.internal._debug" +%} diff --git a/src/sim/debug.cc b/src/sim/debug.cc index be9566836..84ab1074d 100644 --- a/src/sim/debug.cc +++ b/src/sim/debug.cc @@ -93,46 +93,18 @@ DebugBreakEvent::description() return "debug break"; } -// -// Parameter context for global debug options -// -class DebugContext : public ParamContext -{ - public: - DebugContext(const string &_iniSection) - : ParamContext(_iniSection) {} - void checkParams(); -}; - -DebugContext debugParams("debug"); - -VectorParam break_cycles(&debugParams, "break_cycles", - "cycle(s) to create breakpoint events"); - -void -DebugContext::checkParams() -{ - if (break_cycles.isValid()) { - vector &cycles = break_cycles; - - vector::iterator i = cycles.begin(); - vector::iterator end = cycles.end(); - - for (; i < end; ++i) - new DebugBreakEvent(&mainEventQueue, *i); - } -} - // // handy function to schedule DebugBreakEvent on main event queue // (callable from debugger) // -void sched_break_cycle(Tick when) +void +schedBreakCycle(Tick when) { new DebugBreakEvent(&mainEventQueue, when); } -void eventq_dump() +void +eventqDump() { mainEventQueue.dump(); } diff --git a/src/sim/main.cc b/src/sim/main.cc index 6037283a4..17209ac20 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -119,6 +119,7 @@ abortHandler(int sigtype) extern "C" { void init_main(); +void init_debug(); } int @@ -157,8 +158,9 @@ main(int argc, char **argv) Py_Initialize(); PySys_SetArgv(argc, argv); - // initialize SWIG 'm5.internal.main' module + // initialize SWIG modules init_main(); + init_debug(); PyRun_SimpleString("import m5.main"); PyRun_SimpleString("m5.main.main()"); -- cgit v1.2.3