From 9bd0bfe559d8c9633c5686ccf100ab921eb6eda2 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 1 Jul 2008 10:24:09 -0400
Subject: After a checkpoint (and thus a stats reset), the
 not_idle_fraction/notIdleFraction statistic is really wrong. The
 notIdleFraction statistic isn't updated when the statistics reset, probably
 because the cpu Status information was pulled into the atomic and timing
 cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
 care to comment on the odd naming of the Status instance? It shouldn't just
 be status because that is confusing with Port::Status, but _status seems a
 bit strage too.

---
 src/cpu/simple/atomic.cc |  5 +----
 src/cpu/simple/atomic.hh | 13 -------------
 src/cpu/simple/base.cc   |  4 +++-
 src/cpu/simple/base.hh   | 14 ++++++++++++++
 src/cpu/simple/timing.cc |  4 ++--
 src/cpu/simple/timing.hh | 18 ------------------
 6 files changed, 20 insertions(+), 38 deletions(-)

(limited to 'src')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b25d3330f..6b07502ef 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -176,8 +176,6 @@ AtomicSimpleCPU::serialize(ostream &os)
 {
     SimObject::State so_state = SimObject::getState();
     SERIALIZE_ENUM(so_state);
-    Status _status = status();
-    SERIALIZE_ENUM(_status);
     BaseSimpleCPU::serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
@@ -188,7 +186,6 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
     SimObject::State so_state;
     UNSERIALIZE_ENUM(so_state);
-    UNSERIALIZE_ENUM(_status);
     BaseSimpleCPU::unserialize(cp, section);
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 }
@@ -213,7 +210,7 @@ AtomicSimpleCPU::resume()
 void
 AtomicSimpleCPU::switchOut()
 {
-    assert(status() == Running || status() == Idle);
+    assert(_status == Running || _status == Idle);
     _status = SwitchedOut;
 
     tickEvent.squash();
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ccea15073..008397533 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -48,19 +48,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     virtual void init();
 
-  public:
-    //
-    enum Status {
-        Running,
-        Idle,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
   private:
 
     struct TickEvent : public Event
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4a91a9e12..0c1162032 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -174,12 +174,13 @@ void
 BaseSimpleCPU::resetStats()
 {
 //    startNumInst = numInst;
-    // notIdleFraction = (_status != Idle);
+     notIdleFraction = (_status != Idle);
 }
 
 void
 BaseSimpleCPU::serialize(ostream &os)
 {
+    SERIALIZE_ENUM(_status);
     BaseCPU::serialize(os);
 //    SERIALIZE_SCALAR(inst);
     nameOut(os, csprintf("%s.xc.0", name()));
@@ -189,6 +190,7 @@ BaseSimpleCPU::serialize(ostream &os)
 void
 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
+    UNSERIALIZE_ENUM(_status);
     BaseCPU::unserialize(cp, section);
 //    UNSERIALIZE_SCALAR(inst);
     thread->unserialize(cp, csprintf("%s.xc.0", section));
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 918965fdb..62bb31de8 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -129,6 +129,20 @@ class BaseSimpleCPU : public BaseCPU
   protected:
     int cpuId;
 
+    enum Status {
+        Idle,
+        Running,
+        IcacheRetry,
+        IcacheWaitResponse,
+        IcacheWaitSwitch,
+        DcacheRetry,
+        DcacheWaitResponse,
+        DcacheWaitSwitch,
+        SwitchedOut
+    };
+
+    Status _status;
+
   public:
 
 #if FULL_SYSTEM
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d0c7dd787..2cf7d584d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -145,7 +145,7 @@ TimingSimpleCPU::drain(Event *drain_event)
 {
     // TimingSimpleCPU is ready to drain if it's not waiting for
     // an access to complete.
-    if (status() == Idle || status() == Running || status() == SwitchedOut) {
+    if (_status == Idle || _status == Running || _status == SwitchedOut) {
         changeState(SimObject::Drained);
         return 0;
     } else {
@@ -179,7 +179,7 @@ TimingSimpleCPU::resume()
 void
 TimingSimpleCPU::switchOut()
 {
-    assert(status() == Running || status() == Idle);
+    assert(_status == Running || _status == Idle);
     _status = SwitchedOut;
     numCycles += tickToCycles(curTick - previousTick);
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f8b77604a..a748d47b4 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -46,24 +46,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void init();
 
   public:
-    //
-    enum Status {
-        Idle,
-        Running,
-        IcacheRetry,
-        IcacheWaitResponse,
-        IcacheWaitSwitch,
-        DcacheRetry,
-        DcacheWaitResponse,
-        DcacheWaitSwitch,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
     Event *drainEvent;
 
   private:
-- 
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