From 9c49bc7b00aa24b0488a83039ae8762d8f8094c5 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 10 Nov 2008 11:51:17 -0800 Subject: mem: update stuff for changes to Packet and Request --- src/arch/alpha/faults.cc | 2 +- src/arch/alpha/faults.hh | 14 +++++++------- src/arch/alpha/isa/mem.isa | 7 ++++--- src/arch/alpha/isa/pal.isa | 10 +++++----- src/arch/alpha/tlb.cc | 12 ++++++------ src/arch/mips/isa/formats/mem.isa | 6 +++--- src/arch/mips/isa/formats/util.isa | 3 ++- src/arch/mips/tlb.cc | 2 +- src/arch/sparc/isa/formats/mem/swap.isa | 3 +++ src/arch/sparc/tlb.cc | 6 +++--- src/arch/x86/intmessage.hh | 2 +- src/arch/x86/pagetable_walker.cc | 13 ++++++------- src/arch/x86/tlb.cc | 2 +- src/cpu/memtest/memtest.cc | 11 +++++------ 14 files changed, 48 insertions(+), 45 deletions(-) (limited to 'src') diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index dae188839..e89cf5c64 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc) // read, like the EV5). The EV6 approach is cleaner and seems to // work with EV5 PAL code, but not the other way around. if (!tc->misspeculating() && - !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { + reqFlags.none(Request::VPTE|Request::NO_FAULT)) { // set VA register with faulting address tc->setMiscRegNoEffect(IPR_VA, vaddr); diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index 4b107273b..9d90c7719 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -140,11 +140,11 @@ class DtbFault : public AlphaFault { protected: VAddr vaddr; - uint32_t reqFlags; + Request::Flags reqFlags; uint64_t flags; public: - DtbFault(VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags) + DtbFault(VAddr _vaddr, Request::Flags _reqFlags, uint64_t _flags) : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags) { } FaultName name() const = 0; @@ -163,7 +163,7 @@ class NDtbMissFault : public DtbFault static FaultStat _count; public: - NDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags) + NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) : DtbFault(vaddr, reqFlags, flags) { } FaultName name() const {return _name;} @@ -182,7 +182,7 @@ class PDtbMissFault : public DtbFault static FaultStat _count; public: - PDtbMissFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags) + PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) : DtbFault(vaddr, reqFlags, flags) { } FaultName name() const {return _name;} @@ -198,7 +198,7 @@ class DtbPageFault : public DtbFault static FaultStat _count; public: - DtbPageFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags) + DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) : DtbFault(vaddr, reqFlags, flags) { } FaultName name() const {return _name;} @@ -214,7 +214,7 @@ class DtbAcvFault : public DtbFault static FaultStat _count; public: - DtbAcvFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags) + DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) : DtbFault(vaddr, reqFlags, flags) { } FaultName name() const {return _name;} @@ -230,7 +230,7 @@ class DtbAlignmentFault : public DtbFault static FaultStat _count; public: - DtbAlignmentFault(VAddr vaddr, uint32_t reqFlags, uint64_t flags) + DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) : DtbFault(vaddr, reqFlags, flags) { } FaultName name() const {return _name;} diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index fe0daf772..b4e10e849 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -43,7 +43,7 @@ output header {{ protected: /// Memory request flags. See mem_req_base.hh. - unsigned memAccessFlags; + Request::Flags memAccessFlags; /// Pointer to EAComp object. const StaticInstPtr eaCompPtr; /// Pointer to MemAcc object. @@ -54,7 +54,7 @@ output header {{ StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : AlphaStaticInst(mnem, _machInst, __opClass), - memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr) + eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr) { } @@ -677,7 +677,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, inst_flags) if mem_flags: - s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] + s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');' iop.constructor += s memacc_iop.constructor += s diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa index 294b92e2f..3d3b81600 100644 --- a/src/arch/alpha/isa/pal.isa +++ b/src/arch/alpha/isa/pal.isa @@ -174,11 +174,11 @@ output decoder {{ : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr), disp(HW_LDST_DISP) { - memAccessFlags = 0; - if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL; - if (HW_LDST_ALT) memAccessFlags |= ALTMODE; - if (HW_LDST_VPTE) memAccessFlags |= VPTE; - if (HW_LDST_LOCK) memAccessFlags |= LOCKED; + memAccessFlags.clear(); + if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL); + if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE); + if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE); + if (HW_LDST_LOCK) memAccessFlags.set(Request::LOCKED); } std::string diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 9266b8337..be02293d6 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -142,7 +142,7 @@ TLB::checkCacheability(RequestPtr &req, bool itb) return new UnimpFault("IPR memory space not implemented!"); } else { // mark request as uncacheable - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); #if !ALPHA_TLASER // Clear bits 42:35 of the physical address (10-2 in @@ -321,7 +321,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) { //If this is a pal pc, then set PHYSICAL if (FULL_SYSTEM && PcPAL(req->getPC())) - req->setFlags(req->getFlags() | PHYSICAL); + req->setFlags(Request::PHYSICAL); if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) @@ -330,7 +330,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) return NoFault; } - if (req->getFlags() & PHYSICAL) { + if (req->getFlags() & Request::PHYSICAL) { req->setPaddr(req->getVaddr()); } else { // verify that this is a good virtual address @@ -497,13 +497,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } if (PcPAL(pc)) { - mode = (req->getFlags() & ALTMODE) ? + mode = (req->getFlags() & Request::ALTMODE) ? (mode_type)ALT_MODE_AM( tc->readMiscRegNoEffect(IPR_ALT_MODE)) : mode_kernel; } - if (req->getFlags() & PHYSICAL) { + if (req->getFlags() & Request::PHYSICAL) { req->setPaddr(req->getVaddr()); } else { // verify that this is a good virtual address @@ -560,7 +560,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (write) { write_misses++; } else { read_misses++; } uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK; - return (req->getFlags() & VPTE) ? + return (req->getFlags() & Request::VPTE) ? (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), flags)) : (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index f0210c29b..8596308e2 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -43,7 +43,7 @@ output header {{ protected: /// Memory request flags. See mem_req_base.hh. - unsigned memAccessFlags; + Request::Flags memAccessFlags; /// Pointer to EAComp object. const StaticInstPtr eaCompPtr; /// Pointer to MemAcc object. @@ -57,7 +57,7 @@ output header {{ StaticInstPtr _eaCompPtr = nullStaticInstPtr, StaticInstPtr _memAccPtr = nullStaticInstPtr) : MipsStaticInst(mnem, _machInst, __opClass), - memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), + eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), disp(sext<16>(OFFSET)) { } @@ -70,7 +70,7 @@ output header {{ const StaticInstPtr &eaCompInst() const { return eaCompPtr; } const StaticInstPtr &memAccInst() const { return memAccPtr; } - unsigned memAccFlags() { return memAccessFlags; } + Request::Flags memAccFlags() { return memAccessFlags; } }; /** diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index 0405aa5b3..786a964d4 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -61,7 +61,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, inst_flags) if mem_flags: - s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] + s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');' iop.constructor += s memacc_iop.constructor += s diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 7c3b6aed5..e91da4eea 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -149,7 +149,7 @@ TLB::checkCacheability(RequestPtr &req) // or by the TLB entry if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { // mark request as uncacheable - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); } return NoFault; } diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index 2ebe9aa15..046f89822 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -133,6 +133,7 @@ let {{ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] flags = string.join(mem_flags, '|') (header_output, @@ -144,6 +145,7 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{ def format SwapAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, @@ -175,6 +177,7 @@ let {{ def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index b6a450ffe..875ae1411 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -594,7 +594,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) (!write || ce->pte.writable())) { req->setPaddr(ce->pte.translate(vaddr)); if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); return NoFault; } // if matched @@ -607,7 +607,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) (!write || ce->pte.writable())) { req->setPaddr(ce->pte.translate(vaddr)); if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); return NoFault; } // if matched @@ -769,7 +769,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); // cache translation date for next translation cacheState = tlbdata; diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh index 6a5b3aa30..f5f8519e2 100644 --- a/src/arch/x86/intmessage.hh +++ b/src/arch/x86/intmessage.hh @@ -78,7 +78,7 @@ namespace X86ISA prepIntRequest(const uint8_t id, Addr offset, Addr size) { RequestPtr req = new Request(x86InterruptAddress(id, offset), - size, UNCACHEABLE); + size, Request::UNCACHEABLE); PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast); pkt->allocate(); return pkt; diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index e70c16b1d..564a04b38 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -298,11 +298,8 @@ Walker::doNext(PacketPtr &read, PacketPtr &write) } PacketPtr oldRead = read; //If we didn't return, we're setting up another read. - uint32_t flags = oldRead->req->getFlags(); - if (uncacheable) - flags |= UNCACHEABLE; - else - flags &= ~UNCACHEABLE; + Request::Flags flags = oldRead->req->getFlags(); + flags.set(Request::UNCACHEABLE, uncacheable); RequestPtr request = new Request(nextRead, oldRead->getSize(), flags); read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast); @@ -365,8 +362,10 @@ Walker::start(ThreadContext * _tc, Addr vaddr) enableNX = efer.nxe; - RequestPtr request = - new Request(top, size, PHYSICAL | cr3.pcd ? UNCACHEABLE : 0); + Request::Flags flags = Request::PHYSICAL; + if (cr3.pcd) + flags.set(Request::UNCACHEABLE); + RequestPtr request = new Request(top, size, flags); read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast); read->allocate(); Enums::MemoryMode memMode = sys->getMemoryMode(); diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 4980c5fe5..6f1c1a03c 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -653,7 +653,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) return new GeneralProtection(0); */ // Force the access to be uncacheable. - req->setFlags(req->getFlags() | UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr)); } #endif diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 9e5b9d099..3c57f85b7 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -279,7 +279,7 @@ MemTest::tick() unsigned base = random() % 2; uint64_t data = random(); unsigned access_size = random() % 4; - unsigned cacheable = random() % 100; + bool uncacheable = (random() % 100) < percentUncacheable; //If we aren't doing copies, use id as offset, and do a false sharing //mem tester @@ -290,17 +290,16 @@ MemTest::tick() access_size = 0; Request *req = new Request(); - uint32_t flags = 0; + Request::Flags flags; Addr paddr; - if (cacheable < percentUncacheable) { - flags |= UNCACHEABLE; + if (uncacheable) { + flags.set(Request::UNCACHEABLE); paddr = uncacheAddr + offset; } else { paddr = ((base) ? baseAddr1 : baseAddr2) + offset; } - bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE); - //bool probe = false; + bool probe = (random() % 100 < percentFunctional) && !uncacheable; paddr &= ~((1 << access_size) - 1); req->setPhys(paddr, 1 << access_size, flags); -- cgit v1.2.3